CUET PG PYQs for Microprocessors and Interfacing with Solutions: Practice CUET PG Previous Year Questions

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Microprocessors and Interfacing is an important topic in the Data Science A.I Cyber Security and Computer Sci. section in CUET PG exam. Practising this topic will increase your score overall and make your conceptual grip on CUET PG exam stronger.

This article gives you a full set of CUET PG PYQs for Microprocessors and Interfacing with explanations for effective preparation. Practice of CUET PG Data Science A.I Cyber Security and Computer Sci. PYQs including Microprocessors and Interfacing questions regularly will improve accuracy, speed, and confidence in the CUET PG 2026 exam.

CUET PG PYQs for Microprocessors and Interfacing with Solutions

1.
Match List - I with List - II.
List - I List - II
A. Machine cycle I. Time required to complete one operation (Fetch/read/write)
B. T-state II. One subdivision of a machine cycle
C. Instruction cycle III. Time required to complete one instruction
D. Opcode fetch IV. Machine cycle to get instruction opcode from memory
Choose the correct answer from the options given below:

List - I	List - II
A.	Machine cycle	I.	Time required to complete one operation (Fetch/read/write)
B.	T-state	II.	One subdivision of a machine cycle
C.	Instruction cycle	III.	Time required to complete one instruction
D.	Opcode fetch	IV.	Machine cycle to get instruction opcode from memory

A-II, B-III, C-IV, D-I
A-III, B-IV, C-I, D-II
A-I, B-II, C-III, D-IV
A-I, B-II, C-IV, D-III

View Solution

2.
Given below are two statements :
one is labelled as
Assertion (A) and the other is labelled as
Reason (R).
Assertion (A) :
During memory interfacing, address decoding is required to select the desired memory chip.
Reason (R) :
Each memory chip has unique address range that must be enabled using chip select signals.
In the light of the above statements, choose the most appropriate answer from the options given below :
- Both (A) and (R) are correct and (R) is the correct explanation of (A)
- Both (A) and (R) are correct but (R) is not the correct explanation of (A)
- (A) is correct but (R) is not correct
- (A) is not correct but (R) is correct
View Solution
3.
The number of wait states required to interface 8279 to 8086 with an 8MHz clock are:
- 2
- 3
- 1
- 5
View Solution

4.
Match List I with List II.
List I List II
A. Supervisor mode I. Entered when the processor encounters a software interrupt instruction
B. Abort Mode II. Entered in response to memory fault
C. Fast Interrupt Mode III. Entered whenever the processor receives an interrupt signal from a designated fast interrupt source
D. Interrupt Mode IV. Entered whenever the processor receives an interrupt signal from any other source

List I	List II
A. Supervisor mode	I. Entered when the processor encounters a software interrupt instruction
B. Abort Mode	II. Entered in response to memory fault
C. Fast Interrupt Mode	III. Entered whenever the processor receives an interrupt signal from a designated fast interrupt source
D. Interrupt Mode	IV. Entered whenever the processor receives an interrupt signal from any other source

(A) - (III), (B) - (IV), (C) - (II), (D) - (I)
(A) - (I), (B) - (II), (C) - (III), (D) - (IV)
(A) - (II), (B) - (I), (C) - (IV), (D) - (III)
(A) - (IV), (B) - (II), (C) - (I), (D) - (III)

View Solution

5.
Consider the following statements :
A. MOV A, M copies data from memory (pointed by HL) to accumulator

B. LXI H, 2025H loads 2025H into register pair HL

C. STA 2050H stores the accumulator content into memory at address 2050H

D. LDA 2050H loads HL with the contents of memory location at 2050H

Choose the correct answer from the options given below :
- A, B, C only
- B, C, D only
- A, D only
- A, C, D only
View Solution
6.
In case of DMA, after the completion of the transfer, the processor is required to be notified of the completion. This is done through.
- Burst Signal
- Interrupt Signal
- Acknowledgement Signal
- Completion Signal
View Solution
7.
The contents of register BL and register AL of 8085 microprocessor are 49H and 3AH, respectively. The contents of AL, the status of carry flag (CF), and sign flag (SF) after executing the instruction SUB AL, BL are:
- AL = F1H; CF = 1; SF = 1
- AL = 0FH; CF = 1; SF = 1
- AL = F0H; CF = 0; SF = 0
- AL = 1FH; CF = 1; SF = 1
View Solution
8.
Choose the software interrupt from the following list:
- INTR
- RST 6.5
- RST 5
- TRAP
View Solution
9.
After ADI 01H when A = FFH, the accumulator and carry flags are :
- A = 00H, CY = 0
- A = 00H, CY = 1
- A = 01H, CY = 1
- A = FEH, CY = 1
View Solution
10.
Which of the following in 8085 microprocessor performs HL = HL + HL?
- DAD D
- DAD H
- DAD B
- DAD SP
View Solution
11.
After execution of ANI 0FH with accumulator = A9H, which flags are affected ?
- Sign, zero and carry
- Carry and zero
- Zero and parity
- Sign, zero, parity and carry
View Solution
12.
Cycle stealing mode of DMA operation involves:
- DMA controller taking over the address, data, and control buses while a block of data is transferred between memory and I/O device.
- While the microprocessor is executing a program, an interface circuit takes over control of address, data, and control buses when not in use by the microprocessor.
- Data transfer takes place between the I/O device and memory during every alternate clock cycle.
- The DMA control waiting for the microprocessor to finish execution of the program and then takes over the buses.
View Solution
13.
Consider the flags in flag Register from left to right :
A. S

B. Z

C. AC

D. P

E. CY

Choose the correct answer from the options given below :
- A, B, C, D, E
- A, B, D, C, E
- C, D, E, A, B
- C, D, A, B, E
View Solution
14.
Each instruction in an assembly language program has the following fields. What is the correct sequence of these fields?,
(A) Label field
(B) Mnemonic field
(C) Operand field
(D) Comment field
Choose the correct answer from the options given below:
- Label, Mnemonic, Operand, Comment
- Mnemonic, Label, Comment, Operand
- Label, Operand, Mnemonic, Comment
- Mnemonic, Comment, Label, Operand
View Solution

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CUET PG PYQs for Microprocessors and Interfacing with Solutions

3.The number of wait states required to interface 8279 to 8086 with an 8MHz clock are:

6.In case of DMA, after the completion of the transfer, the processor is required to be notified of the completion. This is done through.

7.The contents of register BL and register AL of 8085 microprocessor are 49H and 3AH, respectively. The contents of AL, the status of carry flag (CF), and sign flag (SF) after executing the instruction SUB AL, BL are:

8.Choose the software interrupt from the following list:

9.After ADI 01H when A = FFH, the accumulator and carry flags are :

10.Which of the following in 8085 microprocessor performs HL = HL + HL?

11.After execution of ANI 0FH with accumulator = A9H, which flags are affected ?

12.Cycle stealing mode of DMA operation involves:

13.Consider the flags in flag Register from left to right : A. S B. Z C. AC D. P E. CY Choose the correct answer from the options given below :

14.Each instruction in an assembly language program has the following fields. What is the correct sequence of these fields?,(A) Label field(B) Mnemonic field(C) Operand field(D) Comment fieldChoose the correct answer from the options given below:

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3.
The number of wait states required to interface 8279 to 8086 with an 8MHz clock are:

6.
In case of DMA, after the completion of the transfer, the processor is required to be notified of the completion. This is done through.

7.
The contents of register BL and register AL of 8085 microprocessor are 49H and 3AH, respectively. The contents of AL, the status of carry flag (CF), and sign flag (SF) after executing the instruction SUB AL, BL are:

8.
Choose the software interrupt from the following list:

9.
After ADI 01H when A = FFH, the accumulator and carry flags are :

10.
Which of the following in 8085 microprocessor performs HL = HL + HL?

11.
After execution of ANI 0FH with accumulator = A9H, which flags are affected ?

12.
Cycle stealing mode of DMA operation involves:

13.
Consider the flags in flag Register from left to right :
A. S

B. Z

C. AC

D. P

E. CY

Choose the correct answer from the options given below :

14.
Each instruction in an assembly language program has the following fields. What is the correct sequence of these fields?,
(A) Label field
(B) Mnemonic field
(C) Operand field
(D) Comment field
Choose the correct answer from the options given below: