The Indian Institute of Information Technology (IIITA) is set to conduct a 3-day workshop on ‘Digital Systems & Architecture using Verilog’. As per the brochure released at IIIT Allahabad website, the workshop is scheduled from April 5, 2019, in Dept. of Electronics and Communication Engineering. The registration window is currently open, interested candidates can apply online before March 26, 2019.

Goal of the workshop

The rapid advancement in digital technology and system integration have made possible to design chips with more than a billion transistors. To do so in the digital domain, simulation using hardware description language (HDL) is required.

Of many existing HDL languages, VERILOG is considered to be one of the preferred languages which are also extensively used in Industry/academia for digital embedded systems. A specialized training program has therefore been designed for digital system architecture using VERILOG targeting in-house and external participants. IIIT Allahabad UG students and external UG/PG students from other universities, colleges, and institutions will be benefited by this workshop.

How to Register?

Interested students or faculty members can fill in the registration form available at – Click Here

The application fee for the workshop by IIIT Allahabad is INR 2000 (including accommodation). The confirmation of registration will be notified within 5 days of the submission of the form.

Acceptable modes of Payment

Mode 1: All participants need to send a DD favouring – 'The Director, IIIT Allahabad' payable at Allahabad, before March 26, 2019.

Mode 2: The participants can also pay registration fees through Internet transfer of which the details are:

  • Account Name: 30996838478
  • IFSC Code: SBIN0010891
  • Bank & Branch: State Bank of India, Jhalwa, Allahabad

Day 1 – April 5, 2019

S.No.

Topic

Time

Speaker

1.

Registration and inaugural Session

9:00 am -9:15 am

(-)

2.

Overview of Course, Objective and Latest trends in VLSI Design

9:15 am-10:15 am

IIIT Faculty

Tea Break~ 10:15 am -10:30 am

3.

VLSI Design flow, Design styles, Introduction to FPGA (architecture)

10:30 am -11:30

IIIT Faculty

4.

Digital Design -1

11:30 -12:30 pm

NXP, Semiconductor Noida

5.

Digital Design -2

12:30pm-2:30 pm

Qualcomm, Bangalore

Lunch – 2:30 pm – 3:00 pm

6.

Lab session

12:30 pm – 2:30 pm

Day 2 – April 6, 2019

S.No.

Topic

Time

Speaker

1.

Synchronous digital design-1

9:00 am -10:am

IIIT Faculty

2.

Synchronous digital design-2

10-11:00 am

IIIT Faculty

Tea Break~ 11:00 am -11:15 am

3.

Combinational and Sequential Design

10:30 am -12:30

NXP, Semicondutor, Noida

4.

Combinational and Sequential Design

12:30 -2:30 pm

Qualcomm, Ban galore

Lunch ~ 2:30pm – 3:00pm

5.

Lab session

3:00 pm -6:00 pm

(-)

Day 3 – April 7, 2019

S.No.

Topic

Time

Speaker

1.

FPGA Architecture & Implementation -1

9:00 am -10:am

IIIT Faculty

2.

FPGA Architecture & Implementation -2

10-11:00 am

IIIT Faculty

Tea Break~ 11:00 am -11:15 am

3.

Digital System Design

11:15am -6:00pm

Qualcomm, Ban galore

Helpdesk for the workshop:

For workshop related queries, mail us at​ pro.ruchira@iiita.ac.in

For further information, you may contact the following Coordinators:

Dr. Manish Goswami
M: +91-9792947813
Email: manishgoswami@iiita.ac.in
(OR)
Dr. Prasanna Kumar Misra
M: +91-9838730202)
Email: prasanna@iiita.ac.in