NCERT Exemplar Class 12 Physics Solutions - Class 12 Physics Chapter 14 Free Download

Strategic angle. Contrast metals vs. semiconductors. In a metal n is fixed by valence and only τ matters –- so σ falls with T. In a semiconductor n is thermally activated, so σ rises despite τ falling. The key is to weigh the exponential growth of n against the polynomial decline of τ.

1. Write σ=ne²τ/m for both materials, so dσ/dT depends on the competing trends in n(T) and τ(T).
2. Metals. Valence-band electrons are already free; n is essentially T-independent (∼ 10²⁸ m^-3). Phonon scattering grows with T, so τ↓ as T↑ ⇒ σ↓. This is the positive temperature coefficient of resistance (_R>0) of copper, aluminium, etc.
3. Semiconductors. At T=0 the valence band is full and CB is empty. At finite T, n_i∝ T^3/2e^-E_g/2k_BT. For Si, E_g/2k_B≈ 6400 K, so the exponential dominates: between 300 K and 350 K, n_i rises by roughly a factor of 20.
4. In the same range τ falls only by a factor of ∼ (350/300)^3/2≈ 1.26. The exponential rise in n overwhelmingly dominates ⇒ σ↑ with T, i.e. negative temperature coefficient of resistance.
5. Option (D) packages all three observations: (a) both effects exist, (b) carrier-density rise wins, (c) the relaxation-time fall is real but secondary. Hence (D).

Why this matters. This temperature behaviour is what makes thermistors (semiconductor resistors) useful sensors –- their resistance changes by orders of magnitude over a modest temperature range, while a metal's resistance barely doubles from 0 to 100 .

Option (D).

Strategic angle. Read the barrier as an energy hill that electrons must climb to get from n-side to p-side. Forward bias shortens the hill; reverse bias makes it steeper. The labels in Fig. 14.1 plot the barrier height on the vertical axis, so the visual ordering of the three curves immediately reveals their bias state.

1. Sketch the three barriers on the same axis with V_o marked as the equilibrium reference (curve 2).
2. Imagine connecting an external battery: with the p-side at +V_F, the depletion-region field is partially cancelled, so the barrier sinks to V_o-V_F –- that is the lowest curve.
3. Reverse the battery: p-side at -V_R adds to the built-in field, lifting the barrier to V_o+V_R –- the highest curve.
4. Apply to the labels: 3 is the lowest hill (forward), 1 is the highest hill (reverse), 2 is unbiased. Hence option (B).

Why this matters. The barrier-height picture explains why a diode conducts only in one direction –- only forward bias makes the barrier small enough for thermal carriers (∼ k_BT≈ 0.025 eV) to surmount it in appreciable numbers and produce measurable current.

Option (B).

Strategic angle. Treat each ideal diode as a one-way switch and inspect the polarities at A and B before drawing any current. Two diodes in series, oriented oppositely, can never both conduct simultaneously –- so the circuit is necessarily blocked.

1. Mark potentials: V_A=-10 V, V_B=0 V. Conventional current ``wants'' to flow from B (high potential) to A (low potential), i.e. in the direction B→ A.
2. For B-to-A current to flow, every diode in the path must be forward biased in that same direction. Check each diode arrow against the B→ A direction:
   • D₂: anode at B (0 V), cathode toward A (-10 V). Arrow agrees with B→ A ⇒ forward biased.
   • D₁: anode at A (-10 V), cathode toward B (0 V). Arrow opposes B→ A ⇒ reverse biased.
3. One reverse-biased ideal diode anywhere in the series path is enough to break the circuit; I=0 in steady state.
4. No current also rules out the reverse direction (A→ B): D₂ would be reverse for that direction, again blocking. Hence option (B): D₂ forward, D₁ reverse, zero net current.

Why this matters. Always identify polarities and arrow directions before writing KVL –- many circuit errors come from skipping this check. For ideal diodes, the rule of thumb is: trace the would-be current direction and test each diode arrow against it.

Option (B).

Strategic angle. Recognise the topology as a half-wave peak-detector –- the capacitor is charged to the peak of the AC source through a diode and held there because the diode blocks reverse discharge.

1. Source peak: V_m=√2 V_rms=√2· 220 V=220√2 V≈ 311.1 V.
2. During the first positive half-cycle: v_in rises from 0 toward +V_m, forward-biasing the diode. The capacitor charges through the (negligible) diode resistance until v_C=V_m.
3. During the negative half-cycle: the source falls below v_C, reverse-biasing the diode. With no resistive discharge path (open load), v_C cannot drop –- it stays clamped at V_m.
4. Steady-state DC voltage across the capacitor: V=V_m=220√2 V≈ 311 V. Hence option (D).
5. Order-of-magnitude check: a typical Indian appliance rated at ``220 V AC'' actually sees ± 311 V peaks on its mains terminals. Smoothing capacitors in such gear are rated ≥ 400 V for safety –- consistent with our answer.

Why this matters. This is exactly how DC power supplies first rectify and store mains AC –- a transformer steps the voltage down, then a diode and a smoothing capacitor produce a near-DC peak voltage. The capacitor's job is to ``hold'' the peak until the next positive half-cycle replenishes it.

V=220√2 V –- option (D).

Strategic angle. Pin the definition to the crystal-bond picture, not to vacuum particle physics. A hole is a quasi-particle: a useful collective label for the absence of one electron in an otherwise filled valence band.

1. In silicon, four valence electrons bond with neighbours. Thermal energy at T>0 K can break one such bond, sending an electron into the conduction band and leaving a vacancy in the valence band.
2. The vacancy can be filled by a neighbouring electron, effectively moving the vacancy –- this is exactly the motion of a positive charge carrier of effective charge +e.
3. Identify this object with option-(B): a hole is a vacancy created when an electron leaves a covalent bond.
4. Eliminate the distractors. (A) confuses the hole with the positron –- a true antiparticle exists in vacuum, but a hole is purely a crystal construct. (C) is too vague: the hole sits in the valence band, not in the conduction band where free electrons live. (D) is false because thermal excitation and acceptor doping naturally create holes; nothing artificial is needed.

Why this matters. Hole conduction is just as real as electron conduction –- both carry charge, and Hall-effect measurements directly determine the sign of the dominant carrier. In a p-type semiconductor, holes outnumber electrons by orders of magnitude and dominate the current.

Option (B).

Strategic angle. Trace the loop with the diode's polarity for each half-cycle separately. Do not try to evaluate the rectifier ``on average'' –- the diode is a piecewise device, so case analysis is the only reliable method.

1. Sketch the input v_in=v_msinω t over one full period. Mark the positive half (0 to T/2) and the negative half (T/2 to T).
2. Positive half-cycle. The source's upper terminal goes positive; in Fig. 14.4 this places the diode's cathode at the higher potential and the anode at the lower potential. The diode is reverse biased ⇒ blocks ⇒ v_o=0.
3. Negative half-cycle. Polarities reverse: the diode's anode is now at the higher potential, cathode at the lower. Forward biased ⇒ conducts as a short ⇒ v_o=v_msinω t<0.
4. Average and peak. The output is a train of negative-going half-sinusoids; its DC component is V_DC=-V_m/π (half the magnitude of a full-wave output, with negative sign).
5. Output waveform: negative-only half-sinusoids, matching option (C). (B) is the opposite diode orientation; (D) would need a bridge or centre-tap rectifier; (A) requires both halves blocked, which a single diode cannot achieve.

Why this matters. Reversing the diode in a half-wave rectifier flips the polarity of the DC output without changing anything else. This is how some power supplies generate negative supply rails for op-amps and audio circuits.

Option (C).

Strategic angle. Use KVL: walk from A to B summing every element's drop in order. Diodes contribute a fixed V_f; resistors contribute IR; the current is given so no simultaneous equations are needed.

1. Identify the series chain A→ R→ D→ R→ B carrying I=0.2 mA from A toward B.
2. Apply KVL element-by-element with R=5 kΩ and V_f=0.3 V: V_A-V_B=IR+V_f+IR=2IR+V_f.
3. Substitute numerical values: V_A-V_B=2(0.2× 10^-3)(5× 10³)+0.3=2(1.0)+0.3=2.0+0.3=2.3 V.
4. Match to options: 2.3 V is exactly (B). Option (A) drops one resistor; (C) drops the diode; (D) is unrelated.
5. Sanity check: a sub-mA current through a few-kΩ chain produces a few-volt drop, plus a sub-volt diode addition –- the answer scale is consistent.

Why this matters. Diodes add a fixed voltage drop regardless of the current (to first order) –- this constancy is the basis of voltage-reference circuits, where stacking forward-biased diodes provides a stable bias for transistor stages.

V_A-V_B=2.3 V –- option (B).

Strategic angle. Reduce the combinational circuit to its Boolean expression by tracing each intermediate node. C=A· B from the upper AND, D=A· B from the lower (NOT+AND), and the final OR gives E=C+D=B(A+A)=B. The output cleanly tracks B.

1. Read the topology in Fig. 14.6: A enters the upper AND directly; A is inverted before entering the lower AND; B enters both ANDs; the two AND outputs are combined by an OR to give E.
2. Write the intermediate logic: upper AND output C=A· B; lower AND output D=A· B.
3. Combine through the OR: E=C+D=AB+A B=B(A+A)=B· 1=B. So E=B identically.
4. Build the four rows of the truth table:
   • A=0,B=0: E=B=0.
   • A=0,B=1: E=B=1.
   • A=1,B=0: E=B=0.
   • A=1,B=1: E=B=1.
5. Match against options: 0,1,0,1 is option (C). Options (A) and (B) fail at (0,0); option (D) fails at (1,1).

Why this matters. The algebraic simplification AB+A B=B is a classic case of absorption in Boolean algebra. Recognising such identities lets you replace a multi-gate circuit with a single wire –- the heart of logic minimisation in chip design.

Option (C).

Strategic angle. Remember the band-picture rule: electrons gain energy by going up the energy axis; holes gain energy by going down the same axis (because the hole's effective mass is positive and its energy is measured down from the band edge).

1. Conduction-band electrons. The field exerts a force F=-eE on each electron. In the time between scatterings the electron accelerates against E, gaining kinetic energy. On the E-versus-k diagram, the electron climbs from the band minimum upward ⇒ option (A) is correct, (B) is its opposite and false.
2. Valence-band holes. A hole behaves as a particle of charge +e and is pushed along E. But on the energy axis, a hole's kinetic energy is measured down from the valence-band maximum. So while it gains kinetic energy in the field, the position of the hole on the band diagram moves down. This is option (C); (D) reverses the convention.
3. Both (A) and (C) are correct simultaneously –- they describe the same physical event (drift current) seen from the two carrier perspectives.

Why this matters. The asymmetry of electron and hole motion on the energy axis underlies the direction of drift currents in npn vs. pnp devices. It is also what makes Hall-effect measurements able to distinguish the two carrier types –- electrons and holes deflect to opposite sides of a current-carrying sample.

(A) and (C).

Strategic angle. Follow the electron trajectory: emitter → base → collector. Treat each junction's bias separately and ask: which carriers can cross under this bias?

1. Stage 1 –- forward-biased BE junction. The applied V_BE>0 lowers the BE barrier. The heavily n-doped emitter floods electrons into the thin p-base. So emitter electrons cross into the base ⇒ (C) is true.
2. Stage 2 –- reverse-biased BC junction. The strong reverse field across BC sweeps any electrons that reach the boundary across into the collector. About 95--99% of the injected emitter electrons survive the short base transit and are collected ⇒ (A) is true.
3. Hole behaviour at BC. A reverse bias is reverse for holes too –- holes from the base see an unfavourable field and cannot cross into the collector. So (B) is false.
4. Electron survival in base. The base is deliberately made thin and lightly doped to minimise electron–hole recombination. Far fewer than half the injected electrons leak out via the base contact, so (D) (``leave base without going to collector'') is wrong.
5. Final answer: (A) and (C).

Why this matters. Transistor action requires both a forward BE junction (to inject carriers) and a reverse BC junction (to collect them). Lose either bias and amplification dies –- the very name ``transistor'' was coined from trans-resistor: a current at the input changes a resistance at the output.

(A) and (C).

Strategic angle. Map each V_i value onto one of the three transfer regions before answering. The transfer curve V_o(V_i) is the cleanest visual summary of a CE stage: flat at V_CC in cutoff, sloping downward in active, flat at ≈ 0 in saturation.

1. Mark cutoff | active | saturation boundaries at V_i≈ 0.6 V (cut-in V_BE) and V_i≈ 2 V (where the slope flattens at the bottom of the curve).
2. Bin the four test values: V_i=0.4 V⇒ cutoff; V_i=0.5 V⇒ cutoff; V_i=1 V⇒ active; V_i=2.5 V⇒ saturation.
3. Map each region to its role:
   • Active ⇒ amplifier (large |dV_o/dV_i|, linear operation).
   • Cutoff ⇒ switch off (output high at V_CC).
   • Saturation ⇒ switch on (output low near 0).
4. Score the options:
   • (A) V_i=0.4 V, active –- FALSE (it's in cutoff).
   • (B) V_i=1 V, amplifier –- TRUE (active).
   • (C) V_i=0.5 V, switch off –- TRUE (cutoff).
   • (D) V_i=2.5 V, switch on –- TRUE (saturation).
5. Correct options: (B), (C) and (D).

Why this matters. A single CE transistor functions as either an analog amplifier (active region) or a digital switch cutoff/saturation, depending on the bias. Microprocessors push their billions of transistors deep into cutoff or saturation; audio amplifiers keep them squarely in active.

(B), (C) and (D).

Strategic angle. Apply the two BJT identities in sequence: α definition first, then KCL. ``95% of emitter electrons reach the collector'' is the textbook definition of α=0.95.

1. Identify the data. I_C=10 mA is given; α=0.95 from the 95% statement. The four options ask about I_E and I_B.
2. Step 1 (definition of α). α=I_CI_E I_E=I_Cα=10 mA0.95. Compute: 10/0.95=10.526… mA≈ 10.53 mA. So (B) is true; (A) confuses I_E with some other 8 mA value.
3. Step 2 (KCL at the transistor node). I_E=I_B+I_C I_B=I_E-I_C=10.53-10.00=0.53 mA. So (C) is true; (D) (2 mA) would correspond to α≈ 0.83, far from the given 0.95.
4. Cross-check via β. β=α/(1-α)=0.95/0.05=19. Then I_B=I_C/β=10/19≈ 0.526 mA –- matches the 0.53 mA from KCL within rounding.
5. Final answer: (B) and (C).

Why this matters. The relation I_E=I_B+I_C is the BJT analogue of Kirchhoff's current law at the transistor node, and is the entry point for every BJT bias calculation. The α–β conversion is its companion algebra.

(B) and (C).

Strategic angle. Walk through what depletion means physically: no mobile carriers, only fixed ionic charges, and as a whole the region carries equal totals of positive donor charge and negative acceptor charge. The four options test whether you grasp this picture or are still thinking in terms of free electrons and holes.

1. How the depletion region forms. At the moment the p- and n-sides are joined, mobile electrons from n-side diffuse leftward and mobile holes from p-side diffuse rightward. Where they meet, they recombine.
2. Aftermath of recombination. The region near the junction loses its mobile carriers but is left with the parent donor ions (positive, on n-side) and acceptor ions (negative, on p-side) locked in the crystal lattice.
3. Charge bookkeeping over the full width. Each electron that diffused out of the n-side left behind one donor ion, and each hole that diffused out of the p-side left behind one acceptor ion. The totals must match: N_D W_n=N_A W_p, so integrated over the entire depletion region the positive and negative ionic charges are equal ⇒ the region is electrically neutral as a whole.
4. Score each option against this picture:
   • (A) ``No mobile charges'' –- TRUE; they've recombined or drifted out under the built-in field.
   • (B) ``Equal number of holes and electrons, making it neutral'' –- TRUE in the NCERT-intended reading: the equal totals of positive donor and negative acceptor ionic charge make the region globally neutral, even though there is a local space-charge dipole.
   • (C) ``Recombination has occurred'' –- the cause of the depletion region's formation, but not in the NCERT Exemplar's official answer set.
   • (D) ``Immobile charged ions exist'' –- TRUE; the donor and acceptor ions remain bound to the lattice.
5. Correct options: (A), (B) and (D).

Why this matters. The fixed ionic space charge is exactly what generates the barrier potential V_o and the built-in field that prevents further diffusion at equilibrium. The global charge balance N_D W_n=N_A W_p is the basis of the depletion-width formula for any p–n junction.

(A), (B) and (D).

Strategic angle. A Zener is essentially a voltage clamp: it adjusts its internal (dynamic) resistance to absorb whatever current change is needed to keep V_z fixed. The series resistor R_s ``feels'' the entire fluctuation by carrying a changing current.

1. Anchor the KVL equation: V_in=I_s R_s+V_z, with V_z≈ constant in the breakdown region.
2. Scenario 1: V_in rises. The KVL gives I_s=(V_in-V_z)/R_s –- a larger V_in forces a larger I_s. With load current I_L roughly fixed, the extra current goes into the Zener: I_z=I_s-I_L rises. To keep V_z at the same value while I_z rises, the Zener's incremental resistance falls.
3. Scenario 2: V_in falls. Similarly I_s falls, I_z shrinks, and the Zener's incremental resistance rises. The Zener is dynamically self-adjusting.
4. Score the options:
   • (A) Current in Zener and V_z both fixed –- FALSE: only V_z is roughly fixed; I_z varies with the input.
   • (B) Current through R_s changes –- TRUE (it's the very signature of regulation).
   • (C) Zener resistance constant –- FALSE; it is the change in incremental resistance that achieves regulation.
   • (D) Zener resistance changes –- TRUE.
5. Correct options: (B) and (D).

Why this matters. This is exactly the mechanism behind shunt voltage regulators –- the Zener does the dirty work, sinking variable current so the load sees a steady V_z. The series resistor R_s takes the brunt of the voltage variation.

(B) and (D).

Strategic angle. Use the ripple formula V_r=I_L/(fC)=V_o/(fCR_L) as a checklist: anything that lowers this product lowers ripple. The mnemonic is ``ripple shrinks when the denominator grows.''

1. Recall the ripple formula. Between successive recharge instants the capacitor discharges through the load. The total charge lost in one period is Δ Q=I_L/f; this maps to a voltage drop V_r=Δ Q/C=I_L/(fC)=V_o/(fCR_L).
2. Read the formula as V_r∝ 1/(R_L f C). Every factor in the denominator, when increased, drops the ripple.
3. Score the options:
   • (A) Raise R_L ⇒ less I_L drawn ⇒ less capacitor discharge ⇒ ripple falls. TRUE.
   • (B) Decrease f ⇒ longer discharge interval between peaks ⇒ ripple grows. FALSE.
   • (C) Increase f ⇒ shorter discharge interval ⇒ ripple falls. TRUE.
   • (D) Use larger C ⇒ more stored charge per volt ⇒ ripple falls. TRUE.
4. Numerical sanity check. For V_o=10 V, R_L=1 kΩ, C=100 , f=50 Hz: V_r=10/(50· 100× 10^-6· 1000)=2 V. Doubling C to 200 halves it to 1 V –- consistent with our formula.
5. Correct options: (A), (C) and (D).

Why this matters. Full-wave rectifiers ripple at 2f rather than f –- the rectified waveform has twice as many peaks per second –- so they need only half the capacitance for the same ripple. This is one of the practical reasons FW (or bridge) rectifiers are preferred over half-wave.

(A), (C) and (D).

Strategic angle. Pair the mechanism with the doping regime. Avalanche and Zener are physically distinct breakdown mechanisms; both call themselves ``breakdown'' but rely on opposite microscopic dynamics –- particle-velocity collisions versus field-driven tunnelling.

1. Recall the depletion-width formula: W∝ 1/√N_D N_A/(N_D+N_A). Light doping ⇒ wide depletion region; heavy doping ⇒ narrow depletion.
2. Avalanche mechanism (dominates for light doping). The wide depletion lets minority carriers accelerate over a long distance under the reverse bias, gaining enough kinetic energy to ionise lattice atoms via impact ionisation. Each ionisation produces a new electron–hole pair, which themselves accelerate and ionise further –- a runaway cascade.
3. Zener mechanism (dominates for heavy doping). The narrow depletion concentrates the entire reverse voltage in a ∼ 10 nm layer, producing fields >10⁶ V/cm. This is strong enough that valence electrons can quantum-tunnel directly across the band gap into the conduction band.
4. Score the options:
   • (A) High minority-carrier velocity, low doping ⇒ avalanche. TRUE.
   • (B) High minority-carrier velocity, heavy doping –- pairs avalanche cause with Zener regime. FALSE.
   • (C) Strong field, low doping –- pairs Zener cause with avalanche regime. FALSE.
   • (D) Strong field, heavy doping ⇒ Zener. TRUE.
5. Correct options: (A) and (D).

Why this matters. Zener-effect diodes (low V_z5 V) and avalanche-effect diodes (high V_z7 V) are both sold as ``Zener diodes'' commercially but operate by different microscopic mechanisms –- so their temperature coefficients have opposite signs, an important fact for precision reference designs.

(A) and (D).

Strategic angle. Two criteria must be met simultaneously for a good dopant: right number of valence electrons and right atomic size. Groups XIII and XV uniquely satisfy both.

1. Valence-count criterion. Si/Ge sit in Group XIV with 4 valence electrons. A useful dopant must differ from Si by exactly one electron –- five for n-type (donor) or three for p-type (acceptor). This points directly to Groups XV and XIII.
2. Lattice-fit criterion. The dopant substitutes for a Si atom in the diamond-cubic lattice. If the atomic radius is too different from that of Si (≈ 1.17 ), the dopant introduces strain, dangling bonds, and deep trap states that ruin carrier mobility. Group-XIII (B, Al, Ga, In) and Group-XV (P, As, Sb) elements have radii in the right range.
3. Shallow-level criterion (the payoff). When both criteria are met, the dopant's energy level sits only ∼ 0.01--0.05 eV from the nearest band edge. At room temperature k_BT≈ 0.026 eV, so essentially all dopants are ionised –- carrier density ≈ dopant density.
4. Groups other than XIII and XV either bring the wrong number of electrons (giving deep midgap traps that do not donate carriers at room temperature) or have unsuitable atomic radii.

Why this matters. The shallow donor/acceptor levels created by these dopants (∼0.01–0.05 eV from the band edge) are easily ionised at room temperature, giving useful carrier concentrations of 10¹⁵–10¹⁹ cm^-3 from just 10¹⁵–10¹⁹ dopant atoms per cm³ –- a part-per-billion to part-per-thousand range.

Groups XIII and XV satisfy both the valence-count (± 1 from Group XIV) and size-match criteria.

Strategic angle. It is the band gap, not the valence count, that classifies a solid's electrical behaviour. Group XIV proves this dramatically: all four elements share four valence electrons and the same diamond-cubic crystal structure, yet their electrical character runs the gamut from extreme insulator to metal.

1. Set up the band-gap classification. Insulator: E_g3 eV. Semiconductor: E_g∼ 0.5--2 eV. Conductor: E_g≈ 0 or overlapping bands.
2. Apply to Group XIV, going down the group:
   • Carbon (diamond): E_g≈ 5.5 eV. Far above k_BT at room temperature ⇒ insulator.
   • Silicon: E_g≈ 1.1 eV. Few carriers at room T ⇒ semiconductor.
   • Germanium: E_g≈ 0.67 eV. More carriers ⇒ semiconductor (intrinsic conductivity ∼ 10⁴× that of Si).
   • Tin (grey, α-Sn, below 13.2 ^∘C): E_g≈ 0 eV; white tin (above) is metallic with overlapping bands ⇒ conductor.
3. Why does E_g shrink down the group? Atomic radius grows; outer-shell electrons are less tightly held; bonds weaken; the energy separation between bonding and antibonding bands narrows –- which is exactly E_g.
4. The chemical similarity (all tetrahedral, four valence electrons) gives the same crystal structure; the band-gap trend gives the full electrical spectrum from insulator to conductor.

Why this matters. The chemical similarity in Group XIV gives the same crystal structure (diamond cubic), but the band-gap trend means the same group hosts both the world's hardest insulator (diamond) and a soft metal (tin). The lesson: periodic-table column predicts chemistry, but band gap predicts electrical behaviour.

Band gap decreases down the group: C 5.5 eV (insulator), Si 1.1 eV and Ge 0.67 eV (semiconductors), Sn ≈ 0 (conductor).

Strategic angle. The barrier is electrostatic, not electrochemical –- voltmeter probes need mobile carriers, but the depletion region has none. The very thing that creates the barrier is what prevents you from measuring it directly.

1. Recall how a voltmeter works. It is a high-impedance ammeter: it forces a tiny current (∼ for a digital multimeter, ∼mA for older analog meters) through its internal resistor and computes voltage from the IR drop.
2. Now connect the voltmeter probes across the p–n junction. The instrument tries to push a small current through the depletion region. But that region has no mobile carriers –- only fixed ionic charges –- so no current flows.
3. The instrument's behaviour depends on its internal architecture: it will either show ≈ 0 (because the tiny voltmeter-induced current forward-biases the diode slightly, cancelling most of the barrier) or simply produce an erratic ``OL/open'' reading.
4. Either way the meter does not display V_o. The barrier V_o is a thermodynamic potential maintained by Fermi-level alignment at equilibrium –- it can only be inferred indirectly.
5. How V_o is actually determined. Measure the diode's forward I–V characteristic; the cut-in voltage where current rises sharply (≈ 0.7 V for Si, ≈ 0.3 V for Ge) approximates V_o. Alternatively, use the capacitance-voltage technique for precision device characterisation.

Why this matters. The barrier is inferred from the forward-bias knee voltage on the I–V curve, not from a direct voltmeter reading. This is why every NCERT diagram of a p–n junction draws the V_o label across the depletion region in a band-diagram, never as a voltmeter measurement.

No –- the depletion region's lack of mobile carriers prevents voltmeter current, so the meter cannot read V_o directly.

Strategic angle. Treat each half-cycle separately as a DC analysis with the diode's polarity. A square-wave input simplifies things: the input is piecewise constant, so the output is also piecewise constant.

1. Identify the topology in Fig. 14.8: source → diode → resistor to ground, with output taken across the resistor. The diode points such that conventional current +→- runs from the anode at the source side through the resistor.
2. Half-cycle 1: v_in=+1 V. Anode at +1 V, cathode (after diode, before resistor) drops to 0 V once forward conduction begins. The diode acts as a short; full source voltage appears across the resistor. V_o=v_in=+1 V (ideal diode, zero drop).
3. Half-cycle 2: v_in=-1 V. Anode now at -1 V, cathode at higher potential. Diode is reverse biased; no current ⇒ no drop across the resistor. V_o=0.
4. Output: a unipolar square pulse train of +1 V blocks during positive input phases, 0 V during negative phases. Sketched as the TikZ waveform in the main solution.
5. Sanity check on duty cycle. The input has 50% duty cycle (± 1 V equal durations). The output keeps this 50% high time but at the unipolar level only ⇒ DC average =+0.5 V (half of peak), as expected for a half-wave rectified square wave.

Why this matters. This is exactly the level-shifting + clipping action used in input-protection circuits at logic-gate inputs. The same idea is the front end of half-wave rectifiers feeding pulse trains into digital input pins.

Output: a +1 V pulse during positive input half-cycles, 0 during negative.

Strategic angle. Compute the ideal (theoretical) gain product first, then clip against the available rail. Cascading multiplies voltage gains because each stage's output drives the next stage's input directly.

1. Cascade gain. For amplifiers in series with no inter-stage loss, A_total=A_X· A_Y· A_Z. Substitute: A_total=10× 20× 30=6000.
2. Theoretical (unclipped) output peak: V_out^ideal=A_total· V_in=6000× 1 mV=6 V.
3. Compare with each supply rail.
   • Part (i), V_CC=10 V. Ideal output 6 V<10 V ⇒ headroom available, no clipping. V_o^peak=6 V.
   • Part (ii), V_CC=5 V. Ideal output 6 V>5 V ⇒ the output is clipped at the supply rail. The actual peak is ≈ V_CC=5 V (slightly less because BJTs saturate 0.2--0.5 V below the rail).
4. Interpret the clipping. The amplifier still has gain in the linear region, but the rising sinusoid is flattened at the top once V_o tries to exceed V_CC. Visually, the output is no longer a clean sinusoid but a sine with its top sliced off –- this is harmonic distortion.
5. Sanity check by stage. After stage X: 1 mV× 10=10 mV. After Y: 10 mV× 20=200 mV. After Z: 200 mV× 30=6000 mV=6 V. .

Why this matters. An amplifier's output is bounded by its supply voltage –- a fact often overlooked when stacking gains naively. Hi-fi audio engineers always size the power-supply rails to be larger than the maximum expected signal peak, with a 20--30% headroom margin.

(i) V_o=6 V; (ii) V_o≈ 5 V (clipped at supply rail).

Strategic angle. Identify the true energy source: the DC supply V_CC, not the input signal. The amplifier's ``gain'' is a modulation, not energy creation.

1. Construct the full energy budget. Three power flows touch a CE stage: (i) input AC signal power P_in,AC, (ii) DC supply power P_CC=V_CCI_CC, (iii) output AC power P_out,AC delivered to the load.
2. Map the physical roles.
   • P_in,AC is tiny (mV-level signal across ∼kΩ input impedance, so ).
   • P_CC is much larger (V-level supply, mA-level current, so mW-to-W).
   • P_out,AC is the amplified output –- larger than P_in,AC but smaller than P_CC.
3. Apply conservation: P_CC+P_in,AC=P_out,AC+P_{dissipated as heat in BJT and resistors}. The extra output power on the AC side comes from the DC supply, not from the input signal. The transistor acts as a valve: a small change in I_B (driven by the input) controls a much larger change in I_C (drawn from the supply).
4. Resolve the apparent paradox. ``Voltage gain × current gain = power gain >1'' looks like energy creation only if you ignore the DC supply. Once you include P_CC in the budget, conservation holds exactly.
5. Order-of-magnitude check. Typical small-signal CE: V_CC=10 V, I_C=1 mA, so P_CC=10 mW. Output AC power ∼ 1 mW. Dissipation ∼ 9 mW. Efficiency ≈ 10% –- typical for class-A amplification.

Why this matters. An amplifier is a controlled energy converter, not a free energy source –- this is why every amplifier needs a DC power supply to function, and why class-A audio amplifiers run hot.

No, conservation of energy holds. The extra output power is drawn from the DC supply, not generated by amplification of the input alone.

Strategic angle. Identify each I–V curve by which quadrant the operating region sits in: first-quadrant forward = ordinary diode; sharp third-quadrant reverse-bias knee = Zener; fourth-quadrant operation = solar cell. The quadrant tells you the device.

1. Quadrant map of any p–n junction. Q1 (V>0, I>0): forward conduction, ordinary diode. Q2 not normally accessed. Q3 (V<0, I<0): reverse current, breakdown for Zener. Q4 (V>0, I<0): photovoltaic mode –- the source of output power.
2. Interpret Fig. 14.9(A). The curve shows the standard forward-bias diode action and an abrupt reverse-bias knee at point P. This is the signature of a Zener diode: P corresponds to the reverse breakdown voltage V_z.
3. Interpret Fig. 14.9(B). The curve has a horizontal-then-dropping segment in the fourth quadrant. Reading off:
   • P on the horizontal axis (I=0) marks the open-circuit voltage V_oc –- the voltage when no current flows externally.
   • Q on the vertical axis (V=0) marks the short-circuit current I_sc –- the current when terminals are shorted.
   This Q4 operation, where the cell sources current at positive voltage, is the photovoltaic mode of a solar cell.
4. Summary:
   • (A) is a Zener (or junction diode plotted including the breakdown region); P=V_z.
   • (B) is a solar cell; P=V_oc, Q=I_sc.

Why this matters. The same p–n junction acts as a Zener, photodiode, or solar cell depending on bias and illumination –- the four I–V quadrants tell you which mode it is in. A photodiode under reverse bias is in Q3; turn off the bias and shine light on it and it slides into Q4 to become a solar cell.

(A) Zener (junction diode), P=V_z. (B) Solar cell, P=V_oc, Q=I_sc.

Strategic angle. Compute the photon energy once, then compare against each E_g. The detection rule is binary: detect if E_ph≥ E_g, miss otherwise.

1. Convert wavelength to energy using the standard NCERT shortcut: E_ph=hcλ=1240 eV nmλ(nm). Here λ=6000 =600 nm, so E_ph=1240600 eV=2.067 eV≈ 2.07 eV.
2. Compare E_ph=2.07 eV with each diode's band gap.
   • D₁: E_g=2.5 eV. Is 2.07≥ 2.5? No. Photon lacks energy ⇒ no detection.
   • D₂: E_g=2.0 eV. Is 2.07≥ 2.0? Yes. Photon just exceeds the gap ⇒ detects.
   • D₃: E_g=3.0 eV. Is 2.07≥ 3.0? No. Photon lacks energy ⇒ no detection.
3. Only D₂ detects. The margin is only 0.07 eV above its gap, so D₂ is operating near its long-wavelength edge –- its quantum efficiency at this wavelength would be modest in practice.
4. Cross-check via wavelength threshold. The longest detectable wavelength for D₂ is _max=1240/2.0=620 nm. Our 600 nm is just below this cutoff, confirming detection. For D₁: _max=1240/2.5=496 nm (blue-green). For D₃: _max=1240/3.0=413 nm (violet).

Why this matters. This band-gap selection rule is why visible-light photodetectors use Si (E_g=1.1 eV) or GaAs (1.4 eV) and infrared detectors use narrow-gap materials like InGaAs or HgCdTe. Each wavelength range needs a tailored band gap.

Only D₂ (E_g=2.0 eV) detects, because E_ph=2.07 eV≥ E_g. D₁ and D₃ have band gaps too large for 6000 photons.

Strategic angle. Track the chain of effects: R₁↑ ⇒ I_B↓ ⇒ I_C↓ ⇒ V_CE↑. Each step follows from a single equation, so the reasoning is mechanical once you commit them to memory.

1. Base loop: KVL gives V_BB=I_B R₁+V_BE, so I_B=(V_BB-V_BE)/R₁. Inverse dependence: I_B ∝ 1/R₁. R₁↑ I_B↓.
2. Transistor amplification. The CE stage links I_C to I_B via the current gain β: I_C=β I_B. Hence I_C↓ in lockstep with I_B. The ammeter in the collector branch reads I_C, so its reading decreases.
3. Collector loop. KVL on the collector side: V_CC=I_C R₂+V_CE V_CE=V_CC-I_C R₂. With I_C↓, the term I_CR₂ shrinks, so V_CE rises. The voltmeter reads V_CE and therefore increases.
4. Load-line picture. On the I_C–V_CE characteristic, the operating point slides along the load line from saturation toward cutoff: I_C down, V_CE up. This anti-correlation is the visual signature of CE operation.
5. Limit check. If R₁→∞ (open base), I_B→ 0, I_C→ 0 (cutoff), V_CE→ V_CC –- the transistor fully turns off. Conversely, R₁→ 0 pushes the transistor into saturation, where V_CE→ 0.

Why this matters. The trade-off I_C↔ V_CE along the load line is the fundamental tool for choosing the operating point of any CE stage. A well-biased amplifier sits roughly in the middle of the load line; pushing R₁ too high drives the transistor toward cutoff, killing amplification.

I_C (ammeter) ↓;   V_CE (voltmeter) ↑.

Strategic angle. The English condition (``open when either or both cars enter'') translates directly to the OR truth table. Use the diode-OR topology: it is the simplest passive realisation.

1. Translate the English to logic. ``Open when car in A or car in B or cars in both'' is 00→ 0, 01→ 1, 10→ 1, 11→ 1 –- the standard OR gate.
2. Choose sensors. Inputs A and B come from car-presence sensors (infrared, magnetic, or microswitches) that output a high voltage when a car is present, low otherwise.
3. Construct the diode-OR.
   • Place diode D₁ from input A to a common node Y, anode at A, cathode at Y.
   • Place diode D₂ similarly from B to Y.
   • Connect a resistor R from Y to ground (the pull-down).
   • Y drives the gate-opener relay.
4. Verify the action. If either input is high, its diode forward-conducts, pulling Y up to V_in-V_f≈ V_in (high). The pull-down resistor sinks the tiny leakage but cannot fight the conducting diode. If both inputs are low, both diodes are reverse biased and R holds Y at ground.
5. Truth table check: 00→ 0, 01→ 1, 10→ 1, 11→ 1. OR realised.

Why this matters. Diode logic is fast and simple but cascades poorly –- each stage's output is degraded by one diode V_f, so chaining many gates eventually loses the logic levels. This is why transistor logic (TTL, CMOS) replaced diode logic in modern systems, but the OR principle is identical.

Diode-OR circuit: A→ D₁→ Y, B→ D₂→ Y, with pull-down resistor R from Y to ground; output Y drives the gate-open relay.

Strategic angle. A CE transistor switch is a NOT gate when driven hard between cutoff and saturation. The active region is bypassed; only the two end-points of the transfer curve matter.

1. Circuit recipe. Connect V_CC (+5 V typical) through a collector resistor R_C to the collector terminal. Connect V_in through a base resistor R_B to the base. Tie the emitter to ground. Take the output V_o at the collector.
2. State 1: V_in=0 V (logic ``low''). I<sub>B</sub>=V<sub>in</sub>-V<sub>BE</sub>R<sub>B</sub>≤ 0 transistor in cutoff. With I<sub>C</sub>=0, no drop across R<sub>C</sub>, so V<sub>o</sub>=V<sub>CC</sub>⇒ logic ``high.''
3. State 2: V_in=V_CC (logic ``high''). I<sub>B</sub>=(V<sub>CC</sub>-V<sub>BE</sub>)/R<sub>B</sub> is large enough to drive the transistor into saturation. Saturated BJT has V<sub>CE,sat</sub>≈ 0.2 V, so V<sub>o</sub>≈ 0⇒ logic ``low.''
4. Pick the resistors. For V_CC=5 V and β=100: choose R_C=1 kΩ for I_C∼ 5 mA in saturation, then I_B,sat≈ I_C/β=50 . To drive this with V_in=5 V: R_B=(V_in-V_BE)/I_B,sat=4.3/50 ≈ 86 kΩ. Round down to ∼ 47 kΩ for over-drive margin.
5. Truth table verification: V_in=0⇒ V_o=V_CC (i.e., 0→ 1). V_in=V_CC⇒ V_o≈ 0 (i.e., 1→ 0). This is exactly the NOT gate.

Why this matters. This is the building block of every TTL inverter, every NMOS-like inverter, and ultimately the foundation of every CMOS gate inside your phone's processor. ``NOT'' is the only universal one-input gate, and the CE inverter is its simplest physical realisation.

V_CC→ R_C→ collector; V_in→ R_B→ base; emitter grounded; output at collector. Cutoff ⇒ high output; saturation ⇒ low output. Realises NOT.

Strategic angle. Two independent strikes against elemental Si and Ge as visible-LED materials: band gap too small, and indirect band gap (which kills radiative recombination even at the right energy).

1. Set up the visible-photon energy range. Red (λ=700 nm) corresponds to E_ph=1240/700=1.77 eV. Violet (λ=400 nm) is 1240/400=3.10 eV. So visible photons span roughly 1.8–3.1 eV.
2. Compare with elemental gaps. E_g(Si)=1.1 eV, E_g(Ge)=0.67 eV. Both are below the red threshold, so an electron–hole recombination releases energy in the infrared, not the visible. A Si or Ge LED would emit an invisible IR glow.
3. Indirect band gap (the deeper obstacle). In Si and Ge, the conduction-band minimum and valence-band maximum sit at different crystal momenta k. Radiative recombination must conserve both energy and momentum; the photon has negligible momentum on the lattice scale, so the recombination must borrow momentum from a phonon. This three-body process is much slower than direct recombination ⇒ photon emission is overwhelmingly outcompeted by non-radiative (heat) recombination.
4. Why compound semiconductors win. Direct-gap III–V compounds have CB minimum and VB maximum at the same k (the Γ point), allowing efficient two-body radiative recombination. Their gaps span the visible: GaP E_g=2.26 eV (green–red), GaAs 1.4 eV (near-IR), GaN 3.4 eV UV/blue, AlGaInP alloys cover red–yellow, InGaN covers blue–green.
5. Verdict. Elemental Si/Ge fail on both gap-magnitude (IR not visible) and gap-type (indirect, inefficient). Either failure alone disqualifies them; together the disqualification is overwhelming.

Why this matters. The 1990s blue-LED breakthrough (Nakamura's GaN, awarded the 2014 Nobel Prize) opened white LED lighting –- impossible with silicon technology alone. Compound-semiconductor band-gap engineering is the materials science underlying all modern solid-state lighting.

Both reasons matter: (1) Si and Ge band gaps (1.1 eV and 0.67 eV) are too small for visible photons; (2) both are indirect-gap, so radiative recombination is suppressed. Direct-gap III–V compounds (GaAs, GaP, GaN) are used instead.

Strategic angle. Pull-up resistor + commoned diode cathodes = AND. Pull-down resistor + commoned anodes = OR. Memorise the two templates and you can read off any diode logic at sight.

1. Identify the topology in Fig. 14.11: anodes of D₁, D₂ at inputs A, B; cathodes commoned at output V_o; pull-up resistor from V_o to +5 V. This is the AND template.
2. Trace each input case:
   • A=0, B=0. Both anodes at 0 V; cathode side wants to rise toward +5 but the conducting diodes clamp it to ≈ 0+V_f≈ 0 V. Output low.
   • A=0, B=1. D₁ conducts (anode 0 V, cathode pulled up), clamping output to ≈ 0 V. D₂ may or may not conduct, but its anode at +5 keeps it reverse-biased relative to the clamped output. Output low.
   • A=1, B=0. Symmetric to above: D₂ conducts and clamps output low.
   • A=1, B=1. Both anodes at +5 V. The output, pulled up to +5 V via R, sits at +5 V. Neither diode has positive anode-to-cathode voltage; both are off. Output high.
3. Tabulate. 00:0, 01:0, 10:0, 11:1 –- exactly the AND truth table.
4. Logical expression: V_o=A· B. The circuit realises the Boolean AND gate.

Why this matters. The diode-AND and diode-OR are textbook examples of how voltage-driven logic emerges from simple passive components. They were the very first electronic logic gates (1940s, RAND Corporation, ENIAC era), predating the transistor.

Truth table: 00→ 0, 01→ 0, 10→ 0, 11→ 1. Circuit realises an AND gate.

Strategic angle. The worst-case current happens at maximum input voltage. Size R_s so that even at the worst case, the Zener current stays below its rated maximum.

1. Compute the Zener's maximum allowed current from its power rating: I_z,max=P_ratedV_z=1 W5 V=0.2 A=200 mA. Exceed this and the Zener overheats and fails.
2. Identify worst-case bias. The input swings between 3 V and 7 V. At the high end (V_in,max=7 V) the most current flows through R_s, so this is the limiting case: I_s,max=V_in,max-V_zR_s=7-5R_s=2R_s (A, if $R_s$ in $Ω$).
3. Apply the safety constraint I_s,max≤ I_z,max (worst-case open-load): 2R_s≤ 0.2 R_s≥ 20.2=10 Ω.
4. Address the low-end issue. When V_in=3 Vz=5 v, not in breakdown, so regulation fails: the output simply equals the input minus the R_s drop. This part of the input range is uncovered by Zener regulation; a buck or boost-converter would be needed for a fix.
5. Final answer: R_s≥ 10 Ω. The minimum is 10 Ω for tight operation; a slightly larger value (say 15–22 Ω) provides safety margin against component tolerance.

Why this matters. A Zener regulator's resistor is a sacrificial component –- it must be big enough to protect the Zener at peak input but small enough to keep the regulator load-tolerant. Sizing R_s is the heart of Zener-regulator design.

R_s≥ 10 Ω. (Note: regulation fails when input drops below V_z=5 V.)

Strategic angle. Identify which branches conduct first; once forward/reverse states are nailed down, the rest is routine parallel-combination + Ohm's law.

1. Classify each branch by diode orientation.
   • Branch AB (I₄): diode forward biased. Effective resistance r_f+R=25+125=150 Ω.
   • Branch CD (I₃): diode reverse biased. Effectively open (∞ Ω). Current I₃=0.
   • Branch EF (I₂): diode forward biased. Effective resistance 150 Ω.
2. Compute parallel combination of the two conducting branches: R_par=R_a R_bR_a+R_b=150× 150150+150=22500300=75 Ω.
3. Add the series 25 Ω to the source: R_total=R_series+R_par=25+75=100 Ω.
4. Apply Ohm's law for the main current I₁: I₁=VR_total=5 V100 Ω=0.05 A=50 mA.
5. By the symmetry of the two equal forward branches, I₁ divides equally: I₂=I₄=I₁2=50 mA2=25 mA. And I₃=0 (reverse-biased branch open).
6. Sanity check via KCL at the junction: I₂+I₃+I₄=25+0+25=50 mA=I₁.

Why this matters. Identifying forward vs. reverse biases first is the standard procedure for any diode-network analysis –- skipping it leads to multiplying out infinite resistances or missing zero-current branches.

I₁=50 mA, I₂=I₄=25 mA, I₃=0.

Strategic angle. Two KVL equations, two transistor currents, then divide for β. The peculiarity here is that the transistor is operating in saturation: both V_BE and V_CE are stated to be zero (an idealisation).

1. Recognise the operating point. V_BE=0 and V_CE=0 together mean the transistor is in deep saturation –- both junctions are forward biased.
2. Base loop KVL: V_i=I_B R_p+V_BE. With V_i=10 V, V_BE=0, R_p=400 kΩ: I_B=V_i-V_BER_p=10-0400× 10³ A=2.5× 10^-5 A=25 .
3. Collector loop KVL: V_CC=I_C R_C+V_CE. With V_CC=10 V, V_CE=0, R_C=3 kΩ: I_C=V_CC-V_CER_C=10-03× 10³ A=3.33× 10^-3 A=3.33 mA.
4. Compute the common-emitter current gain: β=I_CI_B=3.33× 10^-325× 10^-6=3.33 mA25 =133.3.
5. Cross-check units: β is dimensionless, as expected. The value β∼ 130 is typical for small-signal silicon BJTs (BC547, 2N3904, etc.).

Why this matters. Knowing β tells you how aggressively the transistor amplifies –- a higher β requires less base drive for the same collector current. In a digital switch, β also sets the minimum base current needed to fully saturate.

I_b=25 ; I_c=3.33 mA; β≈ 133.

Strategic angle. Reduce each gate cluster to its overall logic function before plotting. DeMorgan's laws let you collapse NAND/NOR chains into ordinary AND/OR, after which the waveform plotting is mechanical.

1. Decode the top cluster algebraically. NOT(A)→A, NOT(B)→ B. NAND(A,B)=AB̄=A+B by DeMorgan. So C₁=A OR B.
2. Decode the bottom cluster. NOR(A,B)=A+B̄=A· B by DeMorgan. So C₂=A AND B.
3. Now read the time-segmented inputs from Fig. 14.15. Tabulate A and B on each one-second interval, then compute C₁=A+B and C₂=A· B row by row.
4. Plot the waveforms. C₁ stays high while at least one input is high; C₂ goes high only when both inputs are simultaneously high. From the input traces in Fig. 14.15:
   • C₁ is high from t=0 to 4 s, low from 4 to 5 s.
   • C₂ is high only from t=1 s to 2 s, low elsewhere.
5. Sanity check. Any high pulse on A or B shows up on C₁ (union); only their overlap shows up on C₂ (intersection).

Why this matters. DeMorgan's laws let you build any logic from just NAND or just NOR gates –- the universal-gate property. This is why CMOS chip designers prefer NAND-only (or NOR-only) standard cell libraries: fewer transistor types simplify fabrication.

C₁=A+B (OR): high during 0≤ t≤ 4 s. C₂=A· B (AND): high during 1≤ t≤ 2 s.

Strategic angle. Two KVLs pin down the two resistors; the bias-current gain (β) plus the input impedance r_i give the small-signal voltage and power gains. The whole problem reduces to four short algebra steps once you have the operating-point data.

1. Read the operating point from Fig. 14.16(b): V_CE=8 V, I_C=4 mA, I_B=30 .
2. Base loop KVL: V_BB=I_B R_B+V_BE, so R_B=V_BB-V_BEI_B=16-0.730× 10^-6 Ω=15.33× 10^-5 Ω=5.1× 10⁵ Ω=510 kΩ.
3. Collector loop KVL: V_CC=I_C R_C+V_CE, so R_C=V_CC-V_CEI_C=16-84× 10^-3=84× 10^-3 Ω=2000 Ω=2 kΩ.
4. Current gain: β=I_CI_B=4 mA30 =4× 10^-33× 10^-5=133.3.
5. Small-signal input impedance estimate: r_i≈ V_BE/I_B=0.7/(30× 10^-6)=2.33× 10⁴ Ω≈ 23.3 kΩ.
6. Voltage gain magnitude: |A_v|=β R_Cr_i=133.3×2 kΩ23.3 kΩ=133.3× 0.0858≈ 11.4.
7. Power gain (current gain times voltage gain): A_p=β· |A_v|≈ 133.3× 11.4≈ 1520. Or equivalently A_p≈ 32 dB.
8. Verify against the load line. With R_C=2 kΩ and V_CC=16 V: load line from (V_CE,I_C)=(0, 8 mA) at saturation end to (16,0) at cutoff end. The Q-point (8 V, 4 mA) sits at the midpoint –- maximum symmetric swing without clipping.

Why this matters. Two simple loop equations pin down the bias resistors; the small-signal model then gives gain –- this two-step pattern works for every CE design from radio-frequency low-noise amplifiers to audio output stages.

R_B≈ 510 kΩ; R_C=2 kΩ; β≈ 133; |A_v|≈ 11.4; A_p≈ 1520.

Strategic angle. Diode + DC source = clamp/clipper. Determine the threshold from the battery voltage, then apply piecewise reasoning to each part of the input swing.

1. Identify the diode's switching threshold. The cathode is held at +5 V by the battery. The diode forward-conducts only when its anode (the output node) exceeds the cathode, i.e. when v_out>+5 V.
2. Case 1: v_in≤ +5 V (most of the sine cycle, including all of the negative half and the lower portion of the positive half). Diode is reverse biased ⇒ open circuit. The resistor carries no current to the diode, so the full source voltage appears at the output: v_out=v_in.
3. Case 2: v_in>+5 V (the upper ∼ 30% of the positive half-cycles, near the ± 20 V peaks). Diode is forward biased ⇒ short circuit. The output is clamped to the battery voltage: v_out=+5 V, with the difference v_in-5 dropped across the source resistor.
4. Resulting waveform. Imagine the input sine 20sinω t. Mark a horizontal line at +5 V. Everything below the line passes through unchanged. Everything above is sliced off and replaced by the flat line at +5 V. The negative excursions (-20sinω t) are untouched.
5. Find the time instants of clipping. 20sinω t=5⇒ sinω t=0.25⇒ ω t=14.5^∘ and ω t=165.5^∘ on each cycle. Between these phases (about 42% of the positive half-cycle), the output sits at +5 V.

Why this matters. Positive-peak clippers protect downstream logic from over-voltage spikes –- a common safety circuit at the input of every microcontroller pin. They also generate waveform-shaping effects for audio (guitar distortion pedals exploit precisely this).

Output is the input sine clipped at +5 V on the positive peaks; negative peaks pass through unchanged. Diode + battery form a positive-peak clipper.

Strategic angle. Apply mass-action law to each region, then compare minority concentrations across the junction. The side with the higher minority density dominates the reverse-saturation current.

1. Convert ppm to absolute densities. With N_Si=5× 10²⁸ m^-3: N_D=1 ppm· N_Si=10^-6× 5× 10²⁸=5× 10²² m^-3 (As donor), N_A=200 ppm· N_Si=2× 10^-4× 5× 10²⁸=1× 10²⁵ m^-3 (B acceptor).
2. n-region (bulk wafer, only As doping): n_n≈ N_D=5× 10²² m^-3 (majority), p_n=n_i²n_n=(1.5× 10¹⁶)²5× 10²²=2.25× 10³²5× 10²²=4.5× 10⁹ m^-3 (minority).
3. p-region (surface, both B and As; net acceptor density N_A-N_D): N_A^net=N_A-N_D=10²⁵-5× 10²²≈ 10²⁵ m^-3 (B dominates), p_p≈ N_A^net=10²⁵ m^-3 (majority), n_p=n_i²p_p=2.25× 10³²10²⁵=2.25× 10⁷ m^-3 (minority).
4. Compare minority densities. p_n=4.5× 10⁹ m^-3 in n-region vs. n_p=2.25× 10⁷ m^-3 in p-region. Ratio p_n/n_p=200. The n-region has 200× more minorities than the p-region.
5. Reverse-saturation current. I_S=I_S,p+I_S,n where I_S,p∝ p_n/L_p (holes diffusing from n-to-p) and I_S,n∝ n_p/L_n. Since p_n≫ n_p, the holes crossing from the lightly doped n-region dominate the reverse current.
6. Comment. The lightly-doped (n) side, with its larger minority density, is the leakier side. This is a general design principle: heavy doping on one side suppresses the minority injection from that side.

Why this matters. Reverse-saturation current arises from minority carriers –- the side with more minorities ``leaks'' more, setting the diode's I<sub>S</sub>. This is why ``one-sided'' junctions (p⁺n or pn⁺) are used wherever low reverse leakage matters: the heavily doped side has very few minorities to inject.

n-region: n_n=5× 10²² m^-3, p_n=4.5× 10⁹ m^-3. p-region: p_p≈ 10²⁵ m^-3, n_p=2.25× 10⁷ m^-3. Reverse-saturation current is dominated by holes injected from the n-region (the larger minority).

Strategic angle. Implement each product term with an AND, then sum them with an OR. The two NOT gates supply the bar inputs needed for the products.

1. Set up the target expression: Y=A· B+A· B. This is a sum-of-products (SOP) form with two product terms.
2. Plan the gate count.
   • 2 NOT gates: one for A, one for B.
   • 2 AND gates: one to form A B, one to form AB.
   • 1 OR gate: combines the two product terms.
   • Total: 5 gates.
3. Wire the gates:
   • NOT_A: input A → output A.
   • NOT_B: input B → output B.
   • AND₁: inputs A and B → output A B.
   • AND₂: inputs A and B → output AB.
   • OR: inputs A B and AB → output Y.
4. Verify by exhaustive truth-table check (4 rows):
   • A=0,B=0: A B=0, AB=0, Y=0.
   • A=0,B=1: A B=1, AB=0, Y=1.
   • A=1,B=0: A B=0, AB=1, Y=1.
   • A=1,B=1: A B=0, AB=0, Y=0.
   XOR truth table reproduced exactly.
5. Alternative realisations. XOR can also be built from 4 NANDs alone, or from a single XOR IC (74LS86). The SOP form above is the pedagogical realisation; chip designers use the NAND-only form.

Why this matters. XOR is the basis of parity checkers (detecting single-bit transmission errors) and binary adders (a half-adder's sum output is A⊕ B, its carry is A· B). Every computer's arithmetic unit is built on XOR.

2 NOTs + 2 ANDs + 1 OR realise Y=A⊕ B=A B+AB.

Strategic angle. Each of the six I–V curves reveals one direction's effective network. Pair them up: forward vs. reverse for each terminal pair. Then synthesise the hidden box by matching the observed shapes to canonical I–V signatures.

1. Catalogue the canonical I–V signatures:
   • Pure resistor: straight line through origin, slope 1/R.
   • Forward diode + resistor: zero current until knee at V_f (≈ 0.7 V for Si, 0.3 V for Ge), then linear with slope 1/R.
   • Reverse diode: zero current for all reverse voltages (ideal) or a tiny leakage (real).
   • Diode in parallel with resistor: Ohmic line under reverse bias (resistor only); diode-plus-resistor curve under forward bias.
2. A–B pair.
   • A⁺,B^- (Fig. c): straight line through origin ⇒ resistor present, diode reverse. So in this direction the diode contributes nothing; only the resistor conducts.
   • A^-,B⁺ (Fig. d): knee at 0.7 V + linear rise ⇒ diode forward + resistor.
   Compatible model: between A and B, a 1 kΩ resistor sits in parallel with a Ge diode whose anode is at B (cathode at A). When A⁺ the diode is reverse and the resistor alone conducts. When A^- the diode is forward; resistor and diode conduct simultaneously (the diode dominates above 0.7 V).
3. B–C pair.
   • B^-,C⁺ (Fig. e): knee at 0.7 V, steep rise ⇒ a forward diode (no parallel resistor).
   • B⁺,C^- (Fig. f): line very close to the axis (zero or tiny current) ⇒ reverse diode alone.
   Model: between B and C, a Ge diode with anode at C, cathode at B. No resistor in this branch.
4. A–C pair (sanity check).
   • A⁺,C^- (Fig. g): straight line with the same slope as (c) ⇒ the A–B resistor is in the path; both diodes are reverse ⇒ resistor alone.
   • A^-,C⁺ (Fig. h): knee at 1.4 V (two 0.7 V drops in series!) plus slope ⇒ both diodes forward in series + the resistor.
   This double-knee at 1.4 V confirms the chain: two diodes in series, each contributing 0.7 V.
5. Final arrangement of the box.
   • A–B: 1 kΩ resistor ∥ Ge diode (anode at B).
   • B–C: Ge diode (anode at C).

Why this matters. I–V curve analysis is a black-box characterisation technique –- it lets you reverse-engineer hidden circuits using just an external source and meters. The same method is used to qualify unknown chips and to detect failures in sealed modules.

A–B: 1 kΩ resistor in parallel with a Ge diode (anode at B). B–C: a single Ge diode (anode at C).

Strategic angle. Walk around the main loop for V_E using KVL, then use Ohm's law on R_E and the voltage-divider rule for R_B. The four unknowns (V_E, R_E, V_B, R_B) emerge in sequence, each fed by the previous.

1. Main collector–emitter loop. KVL around the path V_CC→ R_C→ V_CE→ V_E→ ground gives V_CC=I_C R_C+V_CE+V_E. Substitute V_CC=12, I_C=1 mA, R_C=7.8 kΩ, V_CE=3: 12=(1× 10^-3)(7.8× 10³)+3+V_E=7.8+3+V_E=10.8+V_E, V_E=12-10.8=1.2 V.
2. Emitter resistor from Ohm's law (with I_E≈ I_C): R_E=V_EI_E≈ V_EI_C=1.2 V1 mA=1.2 kΩ=1200 Ω.
3. Base voltage from KVL on the base-emitter loop: V_B=V_BE+V_E=0.5+1.2=1.7 V.
4. Base current from the current gain: I_B=I_Cβ=1 mA100=10 .
5. Voltage-divider analysis. The lower divider resistor (20 kΩ) carries the divider current I₂₀=V_B20 kΩ=1.720× 10³=85 . R_B must carry both the divider current and the base current: I_RB=I₂₀+I_B=85+10=95 . Voltage across R_B: V_CC-V_B=12-1.7=10.3 V. Hence R_B=10.3 V95 =10.395× 10^-6 Ω=1.084× 10⁵ Ω≈ 108 kΩ.
6. Sanity check. Sum of resistor drops around the main loop: I_CR_C+V_CE+I_ER_E=(1 mA)(7.8 kΩ)+3+(1 mA)(1.2 kΩ)=7.8+3+1.2=12 V=V_CC.

Why this matters. Emitter degeneration (R_E) stabilises the operating point against temperature and β variations –- this exact divider-bias topology is the workhorse of audio amplifiers, RF front-ends, and discrete instrumentation circuits.

V_E=1.2 V; R_E=1.2 kΩ; R_B≈ 108 kΩ.

Strategic angle. Walk the four-step divider-bias recipe: divider → V_B, V_BE drop → V_E, Ohm's law → I_E≈ I_C, main-loop KVL → R_C.

1. Voltage-divider rule (neglecting base loading, valid when I_B≪ I_divider): V_B=V_CC·20 kΩ100 kΩ+20 kΩ=12·20120=12·16=2 V.
2. Emitter voltage from the V_BE drop: V_E=V_B-V_BE=2-0.5=1.5 V.
3. Emitter (and hence collector) current. With R_E=1 kΩ (the conventional value for this Exemplar setup), I_E=V_ER_E=1.5 V1 kΩ=1.5 mA ≈ I_C.
4. Main loop KVL from V_CC through R_C, V_CE and V_E to ground: V_CC=I_C R_C+V_CE+V_E, 12=I_C R_C+3+1.5=I_C R_C+4.5, I_C R_C=12-4.5=7.5 V.
5. Solve for R_C: R_C=7.5 VI_C=7.51.5× 10^-3 Ω=5000 Ω=5 kΩ.
6. Verify I_B≪ I_divider self-consistency. I_B=I_C/β=1.5 mA/100=15 . I_divider=V_CC/(R₁+R₂)=12/120 kΩ=100 . Ratio I_B/I_divider=15/100=0.15 –- small enough for the divider approximation to hold within ∼ 15%.

Why this matters. The two-loop solution method here scales to any single-stage CE amplifier with emitter degeneration. It also forms the basis for designing the bias network of a more elaborate two-stage or three-stage cascade.

R_C=5 kΩ.