NCERT Solutions Class 12 Physics Chapter 14 Semiconductor Electronics

Numbers that matter. In intrinsic Si at room temperature the carrier density is n_i ≈ 1.510¹⁶ m^-3. With a typical donor doping of 10²² m^-3, the electron density jumps by a factor of about 10⁶. Holes, by the law of mass action n_e n_h = n_i², drop to about 210¹⁰ m^-3 - six orders of magnitude less than the electrons. That huge asymmetry is the whole basis of "majority vs minority" carriers.

Energy-band picture. A pentavalent donor introduces a discrete energy level just below the conduction band donor level, ∼ 0.05 eV below E_c for P in Si. At room temperature this small gap is easily bridged by thermal energy kT ≈ 0.025 eV, so essentially every donor atom is ionised and contributes one free electron.

Common mistake. "n-type" does NOT mean the crystal is negatively charged! The crystal as a whole stays electrically neutral - the donor ion left behind after losing its fifth electron carries a +1 charge that exactly balances the freed electron. The "n" only labels the sign of the majority mobile carrier.

Real world. Almost every chip you own - CPUs, memory, image sensors - is built from precisely engineered n- and p-type regions on a silicon wafer. Modern doping can place donor atoms with atomic-scale accuracy using ion implantation.

What is a "hole"? A hole is not a real particle - it is the absence of an electron in an otherwise filled covalent bond. When a neighbouring electron jumps into that vacancy, the vacancy itself appears to move in the opposite direction. We track it as if it were a positive particle of charge +e and effective mass slightly larger than the electron's.

Acceptor level. A trivalent dopant introduces an empty energy level just above the valence band (acceptor level). Thermal energy easily promotes electrons from the valence band into this level, leaving holes behind in the valence band.

Common mistake. "p-type" does NOT mean the crystal is positively charged. After accepting an electron, the dopant atom becomes a stationary negative ion that balances the mobile hole's charge. The crystal stays neutral overall.

Why we need both types. Modern semiconductor devices (diodes, BJTs, MOSFETs, solar cells, LEDs) all rely on bringing p-type and n-type regions into contact. The p–n junction is the building block of almost all modern electronics.

Why band gap shrinks down a group. Moving down group IV, two effects compound: (i) the lattice constant increases, so the overlap between neighbouring atomic orbitals decreases; (ii) outer valence electrons are screened by more inner shells, weakening their hold on the nucleus. Both push the conduction-band minimum closer to the valence-band maximum.

Conductor vs insulator vs semiconductor in band language.

• Conductor: conduction band partly filled OR overlaps with the valence band E_g = 0. Examples - Cu, Al.
• Insulator: E_g 3 eV. Almost no electrons get thermally excited. Examples - diamond, glass.
• Semiconductor: E_g ≈ 0.2–2 eV. A useful fraction of carriers is thermally excited at room temperature and can be controlled by doping.

Alternate route - Mott's rule of thumb. Optical absorption edge gives E_g. Diamond is transparent right through visible because E_g = 5.4 eV ≫ visible photon energies of 1.6–3.2 eV; Si is opaque to visible light but transparent to infrared because E_g = 1.1 eV corresponds to wavelength ∼ 1100 nm; Ge is transparent to slightly longer IR.

Real world. Si dominates because its band gap is "just right" for room-temperature electronics and it has a tough oxide (SiO₂) for insulation. Ge transistors were used in the 1950s but lost out because of higher leakage. Diamond is being researched as a high-power, high-temperature semiconductor.

The depletion-layer story. When p and n regions are joined, diffusion immediately moves holes p → n and electrons n → p. As soon as a hole crosses, it leaves behind a stationary negative acceptor ion on the p-side; the electron leaves behind a stationary positive donor ion on the n-side. Together, the immobile ions form a depleted region with a built-in electric field pointing from n to p. This field opposes further diffusion. Equilibrium is reached when the diffusion current is exactly cancelled by the drift current driven by the built-in field.

Built-in potential. For Si at room temperature with typical doping the built-in potential is about V₀ = kTe ln(N_A N_Dn_i²) ≈ 0.7 V. This is the "potential barrier" referred to in textbooks.

Common mistake. Don't confuse diffusion (statistical, due to gradient) with drift (electrical, due to field). Diffusion needs no field; drift needs a field. Both currents exist in a p–n junction and balance at equilibrium.

Real world. Every solar cell exploits this: light creates extra electron-hole pairs near the junction, the built-in field separates them, and the resulting current flows through the load.

The diode equation. The full current–voltage relation for an ideal diode is I = I₀(e^eV/kT - 1), where I₀ is the reverse saturation current and V is positive for forward bias, negative for reverse. The exponential dependence on V is what makes diodes such sharp switches: changing V by just 0.06 V at room temperature changes the current by a factor of 10.

Why the barrier shrinks. The applied potential V drops almost entirely across the high-resistance depletion region (the bulk Si has low resistance), so the depletion region itself becomes thinner and the energy step across it shrinks from eV₀ to eV₀ - V.

Common mistake. Forward bias does NOT make minority-carrier flow stop - minority carriers still drift the other way as before. What forward bias does is unleash the much larger majority-carrier current. The net current is overwhelmingly the majority diffusion current.

Real world. The "turn-on" voltage of a Si diode ∼ 0.7 V and of an LED ∼ 2–3.5 V depending on colour is set by the band gap of the semiconductor used.

Why "frequency" of a rectified signal is well-defined. The output isn't a sine wave but a periodic train of pulses; its fundamental frequency is the inverse of the time between successive pulses. For HW that interval equals the input period T; for FW it equals T/2.

Smoothing. Adding a capacitor (or LC) filter across the rectifier output smooths the pulses into a near-DC voltage with small "ripple". The ripple frequency equals the output pulse frequency - 50 Hz for HW, 100 Hz for FW. Full-wave is preferred in power supplies because:

• The filter capacitor recharges twice as often → smaller voltage droop.
• Better transformer utilisation.
• Higher DC content V= 2V_m/π vs V_m/π.

Common mistake. Students sometimes write "frequency = 0 because it's DC". The output is "pulsating DC" - its average is DC, but it still has an AC ripple component at the rectification frequency.

Real world. Your laptop charger uses a bridge rectifier followed by a filter and a switching regulator - the 100 Hz ripple is exactly what the bulky capacitor inside the brick is fighting.

Cut-off wavelength. The longest wavelength the diode can detect is _c = hcE_g = 12402.8 nm ≈ 443 nm. This sits in the violet-blue region of the visible spectrum. Anything redder than 443 nm - including the infrared 6000 nm given in the problem - is invisible to this diode.

Choosing a photodiode. Material selection is dictated by the target wavelength:

• UV/blue: GaN, SiC.
• Visible: Si E_g = 1.1 eV, _c ≈ 1100 nm.
• Near-IR 1.55 fibre telecom: InGaAs.
• Mid-IR (3–14 µm thermal imaging): HgCdTe.

Common mistake. Don't read 6000 nm as 600 nm - the former is mid-IR, the latter is orange visible. A factor of 10 in wavelength changes the photon energy by a factor of 10, which can completely change the answer.

Real world. The same logic explains why Si solar cells lose all sub-1100 nm IR photons - they pass right through. Multi-junction cells stack different-bandgap materials to capture more of the spectrum.

Compensation doping. When both donors and acceptors are present, they "compensate" each other. The net result is determined by whichever dopant has the higher density. Compensation is intentionally used in real chips to fine-tune carrier concentrations: you can over-dope p-type, then back-compensate with donors to land exactly on a target carrier density.

Why n_e ≈ N_D - N_A and not exactly equal. Charge neutrality demands n_e + N_A^- = n_h + N_D⁺. Combined with the mass action law n_e n_h = n_i², this gives the exact quadratic. For our numbers the corrections from n_h and incomplete ionisation are utterly negligible (parts per trillion).

Common mistake. Forgetting the law of mass action and computing n_h directly from N_A. N_A is the acceptor density, not the hole density. In a heavily n-doped sample most acceptors capture electrons from the donor pool and never produce free holes.

Real world. A 13-order-of-magnitude carrier asymmetry is what makes diodes such efficient one-way valves. The reverse saturation current is set by the tiny minority population - about 10⁹ m^-3 here - making leakage in reverse bias minuscule.

Why the factor of 2 in the exponent. Both electrons and holes are created in equal numbers from band-to-band excitation: n_e = n_h = n_i. The probability of an electron jumping from the valence band to the conduction band depends on exp-E_g/k_B T, but n_i ∝ √N_c N_v exp(-E_g/2k_B T) by the law of mass action. That is the origin of the 2k_B T - each carrier "owes" half of the gap energy.

Alternative method - Arrhenius plot. Plot ln σ versus 1/T on a log–linear scale. The slope is -E_g/2k_B; this is the standard experimental way to extract a semiconductor's band gap.

Common mistake. Forgetting the factor of 2: writing σ ∝ exp-E_g/k_B T gives an exponent twice as large and a ratio of ∼ 10¹⁰ - wildly off.

Real world. This dramatic temperature sensitivity is exactly why semiconductors make excellent thermistors and why your phone slows down when it gets hot. It's also why early Ge transistors E_g = 0.7 eV needed heat sinks - even a small temperature rise made the minority current explode.

The "ideality factor". The exercise uses eV/2k_B T, corresponding to an ideality factor n = 2 typical of Si diodes where recombination in the depletion region dominates. The textbook ideal diode (Shockley) uses n = 1. Real Si diodes lie in between depending on the bias regime.

Why current rises ~10× per 0.06 V change. Because e^V/0.0516 = e^{(V+0.06)/0.0516}/e^0.06/0.0516 = e^0.06/0.0516 old ≈ 3.2×. With n=1 V_T = 0.026 the factor is e^0.06/0.026 ≈ 10 per 60 mV - the famous "decade per 60 mV" rule.

Why reverse current saturates. Reverse bias starves the majority-carrier diffusion almost completely; only the few minority carriers generated thermally close to the junction are swept across by the field. Their supply is set by temperature, not by voltage.

Real world. Dynamic resistance of 30 kΩ is huge - but it drops sharply at higher currents. At I = 1 mA, r_d ≈ 2k_B T/(eI) ≈ 50 Ω. That's why diodes are good logarithmic compressors and why the same diode can be used to build temperature sensors.

De Morgan's theorems - the bedrock. A· B̄ = A + B, A + B̄ = A · B. Any logic function whatsoever can be built using only NAND gates or only NOR gates - they are called universal gates. The two circuits in the question are textbook examples of this universality.

Alternative implementation. The AND function in circuit (b) could equally be obtained from two NOR gates via A + B̄ = A· B. The OR function in circuit (a) could be built from two NOR gates by A+B̄̄ = A+B. Try drawing those circuits - they help cement De Morgan.

Common mistake. Confusing the bar levels. Write the expression at each node carefully before applying De Morgan; never apply both bars and a flip simultaneously.

Real world. Inside any CPU, billions of transistors are wired into NAND/NOR cells. The fabrication process is most efficient when only one universal gate type is used; this is why CMOS chips often look like a sea of NAND gates. The OR and AND we use in code reduce, at the silicon level, to constructions exactly like (a) and (b).

Why this trick matters. Among all the basic gates, NAND (and NOR) are the only ones from which every other gate can be built. The very first step in that construction is exactly this one - turn a NAND into a NOT by shorting its inputs. From a NOT and a NAND you can build AND (next problem), and from AND and NOT you can build everything.

Boolean identities at work. A· A = A (idempotent law), Ā = 1 - A. Combined: A· Ā = Ā.

Common mistake. Don't read the diagram as "two independent inputs both set to A" and assume Y is computed by feeding two different probability values. The two inputs are physically the same wire - they cannot disagree.

Real world. In a 7400 series IC, a single quad-NAND chip (7400) can be reconfigured: with input pins shorted in pairs, each NAND becomes a NOT, giving four inverters in one package. Cost-conscious 1970s designers used this trick to avoid stocking a separate 7404 inverter chip.

NAND universality (continued). Together with Q14.12 (NAND → NOT), the two configurations here complete the standard demonstration that any Boolean function can be expressed with NAND alone. By De Morgan,

• NOT A = A· Ā (one NAND).
• AND A· B = A· B̄̄ (two NANDs).
• OR A + B = A· B̄ (three NANDs).

Anything more complex (XOR, mux, flip-flop) is built by composition.

Common mistake. Mis-counting the bars while doing De Morgan. Write each intermediate signal as a Boolean expression at the wire and only then combine.

Real world. The 7400 quad-2-input NAND is the most-produced logic chip in history (introduced 1966). Every introductory digital-electronics lab kit has at least one. Modern FPGAs internally implement every cell with NAND-equivalent transistor networks, exactly because of the universality you have just proved.

NOR universality. Like NAND, NOR is also a universal gate. The standard library:

• NOT: a single NOR with shorted inputs gives A+Ā = A.
• OR: two NORs - first one gives A+B̄, second inverts.
• AND: three NORs - invert each input with one NOR each, then NOR the two inverted signals: A + B̄ = A· B.

Connecting to Q14.13. Compare the structure to Q14.13 circuit (b): both have the pattern "two-input gate → inverter". Replacing NAND by NOR flips AND↔OR. This kind of duality is everywhere in Boolean algebra.

Common mistake. Reading the hint as proof of an OR gate. The hint says Y(0,0)=1 - that is the unique signature of a NOR, since OR would give Y(0,0)=0. Always test 0,0 first when trying to distinguish OR from NOR.

Real world. Early CMOS chips were built from NOR cells because NMOS pull-downs in series (needed for NAND) had higher resistance than parallel pull-downs (needed for NOR). Modern process nodes treat them roughly equally.

The NOR-only toolbox. With just Q14.14, Q14.15(a), and Q14.15(b) you have already constructed NOT, OR, and AND using nothing but NOR. From these three you can build every Boolean function. This is why the original Apollo Guidance Computer (1966) was famously built from only three-input NOR gates on RTL logic - about 5600 of them, doing everything from arithmetic to attitude control to put Apollo astronauts on the Moon.

Alternative method - algebra first, circuit second. For any target function F, first write F in a "NOR-friendly" form using De Morgan: A· B = A + B̄, A + B = A + B̄̄. Each bar becomes a NOR with shorted inputs, each "+ inside a bar" becomes a NOR. Counting NORs gives the gate count directly.

Common mistake. Wiring the inverter NORs to ground or Vcc instead of to the input. Many textbook diagrams show "A → both NOR inputs" - that means the wire is split and both pins of the NOR are connected to A, NOT to ground.

Real world. Modern static-RAM cells use cross-coupled NOR (or NAND) latches as the bit-storage element - a direct descendant of these elementary NOR circuits.