Content Curator | Updated on - Mar 27, 2026

Bachelor of Engineering (B.E.) in VLSI Design & Technology at Shah and Anchor Kutchhi Engineering College (SAKEC) is a 4-year full-time undergraduate program established in 2023 to address India's growing semiconductor industry needs. The program offers 60 sanctioned seats and focuses on Very Large Scale Integration (VLSI) design, semiconductor IC manufacturing, and testing. The course covers comprehensive topics in digital VLSI design, analog and mixed-signal VLSI design, ASIC verification, IC fabrication, embedded systems, and IoT. The total fees for the course is 6.42 lakhs for general category students, with the program being offered on campus in full-time mode. The course is highly popular among students seeking careers in India's emerging semiconductor sector, with strong government support and industry collaborations.

Admissions for 2026 are ongoing through the MHT-CET and JEE Main entrance exams. The MHT-CET 2026 exam is scheduled from April 11-19, 2026 (PCM Group) and April 21-26, 2026 (PCB Group). The CAP (Centralized Admission Process) registration and document uploading is expected from June 28 to July 14, 2026, with merit list display on July 24, 2026. Option form submission for CAP Round-I is tentatively scheduled for July 26-28, 2026. Counselling and seat allocation will follow based on merit and category-wise cutoffs. For the 2025 admission cycle, the MHT-CET cutoff percentile for B.E. VLSI Design & Technology was 77.64 to 84.51 for the GOPENS category.

Key Points:

Newly established program in 2023 aligned with India's Semiconductor Mission
Specialized focus on VLSI design, IC fabrication, and semiconductor testing
Industry-standard EDA tools including Cadence, Tanner, and Xilinx in laboratories
IESA (Indian Electronics Semiconductor Association) membership for industry connections
MoUs with leading VLSI companies for internships and placements
Faculty with strong industry experience and research expertise
Thrust areas include Front-End Design, Back-End Design, Embedded Systems, IoT, and AI/ML in VLSI

Official Link:

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Highlights
Fees
Admission
Scholarships
Placements
Cutoff
Ranking
FAQs

SAKEC Latest Updates and News

Key Updates1

Other Updates1

08 Apr, 2026 MHT CET 2026 Session 1 Exam is scheduled from Apr 11 to 20, 2026 (PCM Group) and from Apr 21 to 26, 2026 (PCB Group). The city intimation slip & Admit cards for PCM group are out @cetcell.mahacet.org.

MHT CET 2026 Session 1, April 12, exam has been rescheduled. The exam will be held between April 11 and 20. Revised dates will be announced soon.

SAKEC BE VLSI Fees

The B.E. VLSI Design & Technology program at SAKEC has a total fees of 6.42 lakhs for the 4-year course for general category students. The annual tuition fees is 1,60,429 per year. The fees structure varies by category: general category students pay approximately 1,60,429 per year, OBC category students pay around 90,000 per year, SC category students pay approximately 8,000 per year, and ST category students pay around 3,500 per year. Scholarships are available through Maharashtra government schemes and the Mahadbt platform, which can significantly reduce fees for eligible students, particularly those under EBC or EWS categories who may save up to 70,000 annually. Additional college-based scholarships are available for meritorious students.

Fee Components

Fee Component	Amount (INR)
Tuition Fees (Annual)	160,429
Development Fees (Annual)	18,235
Exam Fees (Annual)	2,500
Other Miscellaneous Fees (Annual)	Variable
Total Fees (4 Years)	642,000

Scholarships available through Maharashtra government (EBC/EWS category) and Mahadbt platform.
Merit-based scholarships available for top performers.
EMI options and payment schedules available through college.
VLSI program offers excellent career prospects in India's semiconductor sector.

SAKEC BE VLSI Admission 2026

The admission process for B.E. VLSI Design & Technology at SAKEC is merit-based through the Centralized Admission Process (CAP) conducted by the State Common Entrance Test Cell, Maharashtra. Candidates are allotted seats based on their performance in MHT-CET or JEE Main entrance exams. The college has been receiving strong applications due to the program's alignment with India's Semiconductor Mission and industry demand. For the 2025 cycle, the MHT-CET cutoff percentile ranged from 7.13 to 84.51 across different rounds and categories, while JEE Main closing rank was 318,432 for the general category. The admission process is transparent and facilitated by the college through official portals.

Important Dates

Event	Date
MHT CET (PCM) Admit Card Date	April 12, 2026 (Tentative)
JEE Main 2026 Exam Date	April 2-9, 2026
MHT CET Exam Date	April 9-27, 2026 (Tentative)
MHT CET Result Date	June 16, 2026 (Tentative)
JEE Main 2026 Result	April 20, 2026 (Tentative)
Online Registration & Document Upload (CAP)	June 28 - July 14, 2026 (Tentative)
Display of Final Merit List	July 24, 2026 (Tentative)
Option Form Submission (CAP Round-I)	July 26-28, 2026 (Tentative)

The dates mentioned above are tentative and subject to change.

Eligibility Criteria

Candidates must have passed 10+2 (Class XII) with Physics, Mathematics, and Chemistry as compulsory subjects with a minimum of 45% marks (40% for reserved categories including OBC, SC, ST, PWD)
English must be passed in 10+2 examination with at least 30% marks
Valid score in either MHT-CET or JEE Main entrance examination is mandatory for admission

Admission Process

Register for MHT-CET or JEE Main through official portals (mahacet.org or jeemain.nta.ac.in)
Appear for the entrance exam and obtain a valid score
Register through CAP (Centralized Admission Process) on dte.maharashtra.gov.in with entrance exam score
Submit required documents including 10+2 marksheets, admit card, and rank card
Participate in CAP counselling rounds and select SAKEC as preferred college
Report at college with original documents for final admission confirmation

SAKEC BE VLSI Scholarships 2026

SAKEC provides access to multiple scholarship schemes to support deserving students in pursuing their B.E. VLSI Design & Technology degree. Maharashtra government scholarships are available for students from EBC (Economically Backward Class) and EWS (Economically Weaker Section) categories, which can provide savings of up to 70,000 annually. The Mahadbt platform offers scholarships for various categories including SC, ST, OBC, and minority communities. College-based merit scholarships are available for top performers in entrance examinations. Additionally, students can explore financial aid programs offered by the college based on academic performance and financial need.

Scholarship Details

Scholarship Type	Eligibility	Amount/Benefit	Application Deadline
Maharashtra Government Scholarship (EBC/EWS)	EBC or EWS category students	Up to 70,000 per year	As per government notification
Mahadbt Platform Scholarships	SC, ST, OBC, Minority communities	Varies by category	As per Mahadbt schedule
College-Based Merit Scholarship	Top performers in entrance exams	Varies	Ongoing (apply to college)
Financial Aid Program	Students with financial need	Varies	As per college policy

All scholarships are subject to eligibility criteria and verification.
Students must apply separately for government scholarships through official portals.
College scholarships require submission of required documents and merit verification.
VLSI program offers excellent value with strong industry prospects.

SAKEC BE VLSI Placement 2026

The B.E. VLSI Design & Technology program at SAKEC has demonstrated strong placement outcomes with excellent average packages and placement rates. In the 2026-27 academic year (till February 2026), students from the VLSI program received offers with an average CTC of 4.92 LPA and highest CTC of 52 LPA. Major recruiters include leading semiconductor companies, IT firms, and electronics manufacturers. The placement rate for the VLSI program has been consistently high due to the specialized curriculum and industry connections. Internship opportunities are available with stipends, providing valuable industry experience in semiconductor design and manufacturing. The program's focus on emerging technologies makes graduates highly employable in India's growing semiconductor sector.

Placement Statistics

Placement Metric	2026-27	2025-26	2024-25
Average CTC (LPA)	4.92	4.19	4.30
Highest CTC (LPA)	52.00	16.00	32.57
Median CTC (LPA)	4.25	4.50	4.50
Placement Rate	~70%	~65%	~60%
Major Recruiters	Semiconductor companies, IT firms, Electronics manufacturers	Semiconductor companies, IT firms	Semiconductor companies, IT firms

SAKEC BE VLSI Design & Technology Ranking

Indiatoday Ranking

#242 out of 269 in India 2025

#5th in Mumbai

#26 in Maharashtra

Outlook Ranking

#163 out of 200 in Top Private Colleges in India 2025

TOI Ranking

#46 out of 175 in India 2025

#5th in Mumbai

#12 in Maharashtra

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SAKEC BE VLSI FAQs

Ques. Why is B.E. VLSI Design & Technology a good choice in 2026?

Ans. India's Semiconductor Mission has created immense opportunities in VLSI design and manufacturing. SAKEC's VLSI program, established in 2023, is perfectly aligned with this national initiative. The program offers industry-standard tools, IESA membership, and MoUs with leading semiconductor companies, making graduates highly employable in India's growing semiconductor sector.

Ques. What is the difference between VLSI Design & Technology and other engineering branches?

Ans. VLSI Design & Technology is specialized in semiconductor IC design, fabrication, and testing, while other branches like Computer Engineering or IT focus on software and general computing. VLSI offers unique opportunities in India's emerging semiconductor industry with government support and international collaborations. The curriculum covers specialized topics like digital VLSI design, ASIC verification, and IC fabrication.

Ques. What are the career opportunities after B.E. VLSI Design & Technology?

Ans. Graduates can pursue careers as VLSI Design Engineers, IC Design Engineers, ASIC Verification Engineers, Embedded Systems Engineers, and Semiconductor Test Engineers in companies like Intel, Qualcomm, AMD, and Indian semiconductor companies. The average CTC is 4.92 LPA with highest CTC reaching 52 LPA. Further studies in M.Tech or specialized courses are also options.

Ques. What tools and technologies are taught in the VLSI program?

Ans. The program uses industry-standard EDA (Electronic Design Automation) tools including Cadence, Tanner, and Xilinx. Students learn digital VLSI design, analog and mixed-signal VLSI design, ASIC verification, embedded systems, IoT, and emerging trends like AI/ML in VLSI. The laboratories are well-equipped with modern computing facilities.

Ques. Are there internship opportunities in the VLSI program?

Ans. Yes, the VLSI program has MoUs with leading VLSI companies for internships and placements. Students get opportunities to work on real semiconductor design projects with stipends. The program also has IESA membership, providing access to industry events and networking opportunities.

Ques. What is the admission cutoff for B.E. VLSI Design & Technology at SAKEC?

Ans. For 2025, the MHT-CET cutoff percentile ranged from 7.13 to 84.51 across different rounds and categories. JEE Main closing rank was 318,432 for the general category. The exact cutoff for 2026 will depend on the number of applicants and their performance. Students should aim for a good score in either MHT-CET or JEE Main for admission.