Manav Rachna University Faridabad M.Tech Embedded System and VLSI Design: Fees 2026, Course Duration, Dates, Eligibility

Faridabad, HaryanaPrivate UniversityEstd 2004NAAC Grade A++
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Content Curator | Updated 3+ months ago

M.Tech Embedded System and VLSI Design at Manav Rachna University Faridabad is a 2 years, Full Time Degree program offered On Campus.

  • The total fees for the M.Tech Embedded System and VLSI Design program at Manav Rachna University Faridabad is ₹ 2.47 Lakhs.
  • Students need to pay ₹ 1.45 Lakhs in the first year.

According to Collegedunia Engineering Ranking 2025, Manav Rachna University Faridabad ranks 312 out of 762 colleges in India with an overall score of 881 out of 2000. India Today Engineering ranking 2025, ranks Manav Rachna University Faridabad at 74 out of 269 in India.

Find detailed Manav Rachna University Faridabad M.Tech Embedded System and VLSI Design fees, eligibility, admission dates, cutoff and ranking below.

Course HighlightsDetails
duration2 Years (Full Time)
mode of studyOn Campus
total fees₹ 2.9 Lakhs
median package₹ 6 Lakhs
eligibilityGraduation + GATE
entrance testGATE

Manav Rachna University Faridabad Latest Updates and News

28 Sep, 2026 GATE 2027 registration is ongoing @goaps.iitm.ac.in. The registration deadline has been extended to Oct 5, 2026. GATE 2027 will be held between Feb 6 & 21, 2027. Read News.

05 Sep, 2026 Manav Rachna University Admission 2027-28 begins. Interested candidates can apply directly @manavrachna.edu.in. Read more.

Manav Rachna University Faridabad M.Tech Embedded System and VLSI Design Fees

Manav Rachna University Faridabad M.Tech Embedded System and VLSI Design fees 2026 is ₹ 2.47 Lakhs for the entire course duration.
  • This includes a total tuition fee of ₹ 1.58 Lakhs, Other Fees of ₹ 89,800.
  • Candidates need to pay ₹ 1.45 Lakhs in the first year.
  • Manav Rachna University Faridabad Hostel Fee is ₹ 1.6 Lakhs.
Quota:
Fee TypeTotal Amount (INR)
total academic fee₹2.9 Lakhs
hostel fee₹3.21 Lakhs
total fee₹6.11 Lakhs
* Fees is refundable

Important Dates for M.Tech Embedded System and VLSI Design at Manav Rachna University Faridabad

Important Events

EventsDates
GATE 2027 Registration Date
Sep 02, 2026 - Oct 05, 2026
Ongoing
GATE 2027 Admit Card Date
Jan 04, 2027
GATE 2027 Exam Dates
Feb 06, 2027
GATE 2027 Exam Dates
Feb 07, 2027
GATE 2027 Exam Dates
Feb 13, 2027
GATE 2027 Exam Dates
Feb 14, 2027
GATE 2027 Exam Dates
Feb 20, 2027
GATE 2027 Exam Dates
Feb 21, 2027
GATE 2027 Result Date
Mar 19, 2027
Tentative

Expired Events

EventsDates
GATE 2027 Notification
Jul 20, 2026

Important Events

EventsDates
GATE 2027 Registration Date
Sep 02, 2026 - Oct 05, 2026
Ongoing
GATE 2027 Admit Card Date
Jan 04, 2027
GATE 2027 Exam Dates
Feb 06, 2027
GATE 2027 Exam Dates
Feb 07, 2027
GATE 2027 Exam Dates
Feb 13, 2027
GATE 2027 Exam Dates
Feb 14, 2027
GATE 2027 Exam Dates
Feb 20, 2027
GATE 2027 Exam Dates
Feb 21, 2027
GATE 2027 Result Date
Mar 19, 2027
Tentative

Expired Events

EventsDates
GATE 2027 Notification
Jul 20, 2026
Check entrance exam dates for admission in M.Tech Embedded System and VLSI Design at Manav Rachna University Faridabad -

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Manav Rachna University Faridabad M.Tech Embedded System and VLSI Design Admission Process

Eligibility Criteria

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