Work Experience
8.7 yrs
GRE
322

Universities Applied

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Academics & Work Experience

Undergrad Details

Electronics and Communication Engineering
Vellore Institute Of Technology
78%
Aggregate score and pattern

Work Experience(1)

Design Engineer
Full time
Cadence Design Systems
Jan 2018 to Present

Skills(5)

System Verilog
Verilog HDL
C++
Python
UVM