hVw3j0
3wV73y
Select Goal
Work Experience
0.2 yr
GRE
331
Academics & Work Experience
Undergrad Details
Electronics and Communication Engineering
Delhi Technological University
8.21
Aggregate score and pattern
Work Experience(1)
Verification Engineer
Internship
Cadence Design Systems
May 2019 to July 2019 (2 months)
Skills(7)
Verilog HDL
System Verilog
Digital Circuit Design
Vlsi Design
VLSI
Xilinx Vivado
Adobe Premiere Pro
dOGVmW
U76otmw0E9ztwbeABg
xdr+dh 
© 2026 HXW3Qr