Mina Dhar - Study Abroad profile

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Work Experience

7.1 yrs

GRE

323

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admitted

admitted

Applied Date: 26 Dec 2019

Decision: 27 Mar 2020

admitted

Applied Date: 27 Dec 2019

Decision: 05 Feb 2020

Electronics and Communication Engineering

Rajagiri School Of Engineering And Technology

7.84

Aggregate score and pattern

Vlsi Engineer

Full time

Wipro Technologies

Oct 2017 to Present

VLSI

Verilog HDL

System Verilog

Synopsys EDA Tools

Cadence EDA Tool

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