St. Joseph's College of Engineering and Technology Palai M.Tech Embedded System and VLSI Design: Fees 2026, Course Duration, Dates, Eligibility

Kottayam, KeralaEstd 2002 MG University, Kottayam NAAC Grade A
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Collegedunia Team

Content Curator | Updated 3+ months ago

M.Tech Embedded System and VLSI Design at St. Joseph's College of Engineering and Technology Palai is a 2 years, Full Time Degree program offered On Campus. It offers a limited number of 120 seats.

  • The total fees for the M.Tech Embedded System and VLSI Design program at St. Joseph's College of Engineering and Technology Palai is ₹ 2.88 Lakhs.
  • Students need to pay ₹ 1.44 Lakhs in the first year.

Find detailed St. Joseph's College of Engineering and Technology Palai M.Tech Embedded System and VLSI Design fees, eligibility, admission dates, cutoff and ranking below.

Course HighlightsDetails
duration2 Years (Full Time)
mode of studyOn Campus
total fees₹ 2.88 Lakhs
eligibilityGraduation + GATE

St. Joseph's College of Engineering and Technology Palai Latest Updates and News

02 Sep, 2026 GATE 2027 registration begins. Register @goaps.iitm.ac.in by Sept 27, 2026. GATE 2027 will be held between Feb 6 & 21, 2027. Read News.

St. Joseph's College of Engineering and Technology Palai M.Tech Embedded System and VLSI Design Fees

M.Tech Embedded System and VLSI Design Fees at St. Joseph's College of Engineering and Technology Palai covers a range of expenses, including tuition fee, course materials, and access to campus facilities.
  • The total fees for M.Tech Embedded System and VLSI Design is ₹ 2.88 Lakhs.
  • This includes a total tuition fee of ₹ 2.88 Lakhs.
  • Candidates need to pay ₹ 1.44 Lakhs in the first year.

Earlier, M.Tech Embedded System and VLSI Design fees at St. Joseph's College of Engineering and Technology Palai was ₹ 1.2 Lakhs (in 2025) for the entire course duration. This shows a fee increase of ₹ 1.68 Lakhs over the year.

Quota:
Fee TypeTotal Amount (INR)
tuition fee₹2.88 Lakhs
total academic fee₹2.88 Lakhs
hostel fee₹55,000
total fee₹3.43 Lakhs
* Fees is refundable

Important Dates for M.Tech Embedded System and VLSI Design at St. Joseph's College of Engineering and Technology Palai

Important Events

EventsDates
GATE 2027 Registration Date
Sep 02, 2026 - Sep 27, 2026
Ongoing
GATE 2027 Admit Card Date
Jan 04, 2027
GATE 2027 Exam Dates
Feb 06, 2027
GATE 2027 Exam Dates
Feb 07, 2027
GATE 2027 Exam Dates
Feb 13, 2027
GATE 2027 Exam Dates
Feb 14, 2027
GATE 2027 Exam Dates
Feb 20, 2027
GATE 2027 Exam Dates
Feb 21, 2027
GATE 2027 Result Date
Mar 19, 2027
Tentative

Expired Events

EventsDates
Admission Timeline [ME/M.Tech]
May 15, 2026 - Aug 29, 2026
GATE 2027 Notification
Jul 20, 2026

Important Events

EventsDates
GATE 2027 Registration Date
Sep 02, 2026 - Sep 27, 2026
Ongoing
GATE 2027 Admit Card Date
Jan 04, 2027
GATE 2027 Exam Dates
Feb 06, 2027
GATE 2027 Exam Dates
Feb 07, 2027
GATE 2027 Exam Dates
Feb 13, 2027
GATE 2027 Exam Dates
Feb 14, 2027
GATE 2027 Exam Dates
Feb 20, 2027
GATE 2027 Exam Dates
Feb 21, 2027
GATE 2027 Result Date
Mar 19, 2027
Tentative

Expired Events

EventsDates
GATE 2027 Notification
Jul 20, 2026
Check entrance exam dates for admission in M.Tech Embedded System and VLSI Design at St. Joseph's College of Engineering and Technology Palai -

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St. Joseph's College of Engineering and Technology Palai M.Tech Embedded System and VLSI Design Admission Process

Eligibility Criteria
Seat Intake

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